k4x56163pe-lg Samsung Semiconductor, Inc., k4x56163pe-lg Datasheet - Page 14

• Manufacturer Part Number: k4x56163pe-lg
• Description: 16m X16 Mobile Ddr Sdram
• Manufacturer: Samsung Semiconductor, Inc.

The following functionality establishes how a Write command may interrupt a Read burst.
1.
DQ bus prior to valid input write data. Once the Burst Terminate command has been issued, the minimum delay to a Write command
= RU(CL) [CL is the CAS Latency and RU means round up to the nearest integer].
2.
K4X56163PE-L(F)G
CAS Latency=3
Read Interrupted by a Read
A Burst Read can be interrupted before completion of the burst by new Read command of any bank. When the previous burst is
interrupted, the remaining addresses are overridden by the new address with the full burst length. The data from the first Read com-
mand continues to appear on the outputs until the CAS latency from the interrupting Read command is satisfied. At this point the data
from the interrupting Read command appears. Read to Read interval is minimum 1 Clock.
Read Interrupted by a Write & Burst Stop
To interrupt a burst read with a write command, Burst Stop command must be asserted to avoid data contention on the I/O bus by
placing the DQs(Output drivers) in a high impedance state. To insure the DQs are tri-stated one cycle before the beginning of the
write operation, Burst stop command must be applied at least 2 clock cycles for CL=2 and at least 3 clock cycles for CL=3 before the
Write command.
CAS Latency=3
Command
Command
CK, CK
CK, CK
DQS
DQs
< Burst Length=4, CAS Latency=3 >
It is illegal for a Write command to interrupt a Read with autoprecharge command.
< Burst Length=4, CAS Latency=3 >
For Write commands interrupting a Read burst, a Burst Terminate command is required to stop the read burst and tristate the
DQS
DQs
READ A
READ
0
0
Figure.8 Read interrupted by a write and burst stop timing.
Burst Stop
READ B
1
1
Figure.7 Read interrupted by a read timing
Preamble
Preamble
NOP
NOP
t
RPRE
t
RPRE
2
2
t
t
SAC
SAC
Dout A
Dout 0 Dout 1
NOP
NOP
0
3
3
Dout A
14
1
Dout B
NOP
NOP
0
4
4
Dout B
1
Dout B
WRITE
NOP
t
WPRES
2
5
5
Dout B
t
DQSS
t
Mobile-DDR SDRAM
WPREH
3
NOP
NOP
Din 0
6
6
Din 1
NOP
NOP
Din 2
7
7
Din 3
March 2004
NOP
8
8