M25P10-AVMB3/X NUMONYX [Numonyx B.V], M25P10-AVMB3/X Datasheet - Page 9

• Manufacturer Part Number: M25P10-AVMB3/X
• Description: 1 Mbit, serial Flash memory, 50 MHz SPI bus interface
• Manufacturer: NUMONYX [Numonyx B.V]

M25P10-A
3
Figure 3.
1. The Write Protect (W) and Hold (HOLD) signals should be driven, High or Low as appropriate.
SPI interface with
(CPOL, CPHA) =
CS3
(0, 0) or (1, 1)
SPI Bus Master
SPI modes
These devices can be driven by a microcontroller with its SPI peripheral running in either of
the two following modes:
●
●
For these two modes, input data is latched in on the rising edge of Serial Clock (C), and
output data is available from the falling edge of Serial Clock (C).
The difference between the two modes, as shown in
bus master is in Standby mode and not transferring data:
●
●
Bus master and memory devices on the SPI bus
Figure 3
device is selected at a time, so only one device drives the Serial Data output (Q) line at a
time, the other devices are high impedance. Resistors R (represented in
that the M25P10-A is not selected if the Bus Master leaves the S line in the high impedance
state. As the Bus Master may enter a state where all inputs/outputs are in high impedance
at the same time (for example, when the Bus Master is reset), the clock line (C) must be
connected to an external pull-down resistor so that, when all inputs/outputs become high
impedance, the S line is pulled High while the C line is pulled Low (thus ensuring that S and
C do not become High at the same time, and so, that the t
typical value of R is 100 kΩ , assuming that the time constant R*C
capacitance of the bus line) is shorter than the time during which the Bus Master leaves the
SPI bus in high impedance.
CS2
CPOL=0, CPHA=0
CPOL=1, CPHA=1
C remains at 0 for (CPOL=0, CPHA=0)
C remains at 1 for (CPOL=1, CPHA=1)
CS1
shows an example of three devices connected to an MCU, on an SPI bus. Only one
SDO
SDI
SCK
R
R
C Q D
S
SPI memory
device
W
V
CC
HOLD
V
R
SS
C Q D
S
SPI memory
device
Figure
W
V
HOLD
CC
SHCH
4, is the clock polarity when the
V
R
SS
requirement is met). The
p
(C
C Q D
S
p
SPI memory
= parasitic
device
Figure
W
V
CC
3) ensure
HOLD
AI12836b
SPI modes
V
SS
V
V
CC
SS
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