STE100P_06 STMICROELECTRONICS [STMicroelectronics], STE100P_06 Datasheet
STE100P_06
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STE100P_06 Summary of contents
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FAST ETHERNET 3.3V TRANSCEIVER 1 DESCRIPTION The STE100P, also referred to as STEPHY1 high performance Fast Ethernet physical layer in- terface for 10Base-T and 100Base-TX applica- tions. It was designed with advanced CMOS technology to provide a ...
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STE100P 2.2 Physical Layer Integrates the whole Physical layer functions of 100Base-TX and 10Base-T ■ Provides Full-duplex operation on both 100Mbps and 10Mbps modes ■ Provides Auto-negotiation(NWAY) function of full/half duplex operation for both 10 and 100 Mbps ■ Provides ...
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PIN ASSIGNMENT DIAGRAM Figure 4. Pin Connection 64 1 mf4 2 mf3 3 mf2 4 mf1 5 mf0 6 fde 7 gnda vcca gnda vcca 14 gnda iref 15 vcca ...
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STE100P Table 2. Pin Description (continued) Pin No. Name Type 52 tx_er I 51 rxd4 O 43 rxd3 44 rxd2 46 rxd1 47 rxd0 48 rx_dv O 51 rx_er O 49 rx_clk O 59 col O 60 crs O MII ...
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Table 2. Pin Description (continued) Pin No. Name Type 15 iref O 38 ledr10 I/O 37 ledtr 36 ledl I/O 35 ledc I/O 34 leds I/O 64 cfg0 I 63 cfg1 I 28 reset I 29 rip O 8, 30,31, ...
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STE100P Table 2. Pin Description (continued) Pin No. Name Type 5 mf0 I 4 mf1 3 mf2 2 mf3 1 mf4 6 fde I Digital Power Pins 39, 45, 62 25, 40, 50 Analog Power Pins 9, 13, 16, 17, ...
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HARDWARE CONTROL INTERFACE 5.1 Operating Configurations The Hardware Control Interface consists of the MF<4:0>, CFG <1:0> and FDE input pins as well as the LED/PAD pins. This interface is used to configure operating characteristics of the STE100P. The Hard- ...
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STE100P 6 REGISTERS AND DESCRIPTORS DESCRIPTION There are 11 registers with 16 bits each supported for the STE100P. These include 7 basic registers which are defined according to the clause 22 “Reconciliation Sublayer and Media Independent Interface” and clause 28 ...
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Table 5. Register Descriptions (continued) Bit # Name 11 PDEN Power-down mode control. 1: Power-down mode is selected. Setting this bit puts the STE100P into power-down mode. During the power-down mode, TXP/TXN and all LED outputs are 3-stated, and the ...
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STE100P Table 5. Register Descriptions (continued) Bit # Name 6 MFPS MF Preamble Suppression 1 =Accepts management frames with pre-amble suppressed Will not accept management frames with preamble suppressed. The value of this bit is controlled by bit ...
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Table 5. Register Descriptions (continued) Bit # Name 13 RF Remote Fault function. 1: with remote fault function. 12,11 --- Reserved 10 FC Flow Control function Ability. 1:supports PAUSE operation of flow control for full duplex link 100BASE-T4 ...
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STE100P Table 5. Register Descriptions (continued) Bit # Name 5 LP10H Link Partner’s 10Base-T Half Duplex ability. 0: link partner without 10Base-T ability. 1: link partner with 10Base-T ability. 4~0 LPSF Link partner select field. Default 00001=IEEE 802.3. PR6- ANE, ...
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Table 5. Register Descriptions (continued) Bit # Name 3 ANAR Interrupt source of Auto-Negotiation Acknowledge Received. 0: there is no link code word received. 1: link code word is receive from link partner. 2 PDF Interrupt source of Parallel Detection ...
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STE100P Table 5. Register Descriptions (continued) Bit # Name 11, 10 --- reserved 9 ENRLB Enable remote loop-back function. 1: enable 8 ENDCR Enable DC restoration. 0: disable DC restoration. 1: enable DC restoration. 7 ENRZI Enable the conversions between ...
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Table 5. Register Descriptions (continued) Bit # Name 7~3 PAD4:0 PHY Address [4:0]: The values of the PAD[4:0] pins are latched to this register at power-up/reset. The first PHY address bit transmitted or received is the MSB of the address ...
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STE100P Data conversion of Parallel to Serial, NRZ to NRZI, NRZI to MLT3: After scrambled, the transmission data with 5B type in 25MHz will be converted to serial bit stream in 125MHz by the parallel to serial func- tion. After ...
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Loop-back Operation The STE100P provides internal loop-back option for both the 100Base-TX and 10Base-T operations. Set- ting bit 14 of PR0 register to 1 can enable the loop-back option. In this loop-back operation, the txp/txn and rxp/rxn lines are ...
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STE100P 7.9 LED Display Operation The STE100P provides 5 LED pins, the detail descriptions about the operation are described in the PIN Description section, and as follows. Speed LED: 100Mbps(on) or 10Mbps(off) ■ Receive LED: Blinks at 10Hz when receiving, ...
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Note: The above LED connections are recommended for setting a Logic Level 1 or Logic Level 0 on the STE100P LED/PHY Address pins, for determining PHY address. 7.11 Preamble Suppression Preamble suppression mode in the STEPHY1 is indicated by a ...
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STE100P 8 ELECTRICAL SPECIFICATIONS AND TIMINGS Table 6. Absolute Maximum Ratings Parameter Supply Voltage(Vcc) Input Voltage Output Voltage Storage Temperature Ambient Temperature ESD Protection Table 7. General DC Specifications Symbol Parameter General DC Vcc Supply Voltage 10Base-T Voltage/Current Characteristics Vida10 ...
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Table 8. AC Specifications Symbol Parameter X1 Specifications TX1d X1 Duty Cycle TX1p X1 Period TX1t X1 Tolerance TX1C X1 Load Capacitance L 10Base-T Normal Link Pulse (NLP) Timings Specifications TNPW NLP Width TNPC NLP Period Figure 8. Normal Link ...
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STE100P Figure 9. Fast Link Pulse timing Tflbw Table 8. AC Specifications Symbol Parameter 100Base-TX Transmitter AC Timings Specification Tjit TDP-TDN Differential Output Peak Jitter MII Management Clock Timing Specifications t1 MDC High Pulse Width t2 MDC Low Pulse Width ...
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Figure 10. MII Management Clock Timing MDC MDIO(I) MDIO(O) Table 8. AC Specifications Symbol Parameter MII Receive Timing Specification t1 RX-ER, RX-DV, RXD[3:0] Setup to RX-CLK t2 RX-ER, RX-DV, RXD[3:0] Hold After RX-CLK t3 RX-CLK High Pulse Width (100 Mbits/s) ...
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STE100P Figure 11. MII Receive Timing Table 8. AC Specifications Symbol Parameter MII Transmit Timing Specification t1 TX-ER,TX-EN,TXD[3:0] Setup to TX-CLK Rise t2 TX-ER,TX-EN,TXD[3:0] Hold After TX-CLK Rise Figure 12. MII Transmit Timing 24/31 Test Condition Min Typ. ...
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Table 8. AC Specifications Symbol Parameter Receive Timing Specification Rt1 Receive Frame to Sampled Edge of RX-DV (100 Mbits/s) Receive Frame to Sampled Edge of RX-DV (10 Mbits/s) Rt2 Receive Frame to CRS High (100Mbits/s) Receive Frame to CRS High ...
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STE100P Table 8. AC Specifications Symbol Parameter Transmit Timing Specification t1 TX-EN Sampled to CRS High (100 Mbits/s) TX-EN Sampled to CRS High (10 Mbits/s) t2 TX-EN Sampled to CRS Low (100 Mbits/s) TX-EN Sampled to CRS Low (10 Mbits/s) ...
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Figure 15. 100BaseT Transmit Timing TXP Table 9. Parameter TXD, TX_EN, TX_ER Setup to TX_CLK High TXD, TX_EN, TX_ER Hold from TX_CLK High TX_EN sampled to CRS asserted TX_EN sampled to CRS de-asserted TX_EN sampled to TXP out (Tx latency) ...
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STE100P Figure 16. 10Base-T Half Duplex Transmit Timing TXP Table 10. Parameter TXD, TX_EN, TX_ER Setup to TX_CLK High TXD, TX_EN, TX_ER Hold from TX_CLK High TX_EN sampled to CRS asserted TX_EN sampled to CRS de-asserted TX_EN sampled to TXP ...
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PACKAGE INFORMATION In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box ...
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STE100P Table 11. Revision History Date Revision January 2004 June 2004 August 2004 September 2004 February 2005 30/31 15 Rev. A12 June 2003 has been migrated from ST-PRESS to EDOCS. 16 Changed the Style-sheet on the Rev. A13. 17 Wrong ...
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. ...