STE36N50A STMICROELECTRONICS [STMicroelectronics], STE36N50A Datasheet

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STE36N50A

Manufacturer Part Number
STE36N50A
Description
N - CHANNEL ENHANCEMENT MODE POWER MOS TRANSISTOR IN ISOTOP PACKAGE
Manufacturer
STMICROELECTRONICS [STMicroelectronics]
Datasheet

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Part Number:
STE36N50A
Manufacturer:
ST
0
ABSOLUTE MAXIMUM RATINGS
( ) Pulse width limited by safe operating area
September 1994
STE36N50A
INDUSTRIAL APPLICATIONS:
Symbol
I
HIGH CURRENT POWER MODULE
AVALANCHE RUGGED TECHNOLOGY
VERY LARGE SOA - LARGE PEAK POWER
CAPABILITY
EASY TO MOUNT
SAME CURRENT CAPABILITY FOR THE
TWO SOURCE TERMINALS
EXTREMELY LOW R
VERY LOW DRAIN TO CASE CAPACITANCE
VERY LOW INTERNAL PARASITIC
INDUCTANCE (TYPICALLY < 5 nH)
ISOLATED PACKAGE UL RECOGNIZED
(FILE No E81743)
SMPS & UPS
MOTOR CONTROL
WELDING EQUIPMENT
OUTPUT STAGE FOR PWM, ULTRASONIC
CIRCUITS
V
D M
V
V
V
P
T
DG R
I
I
T
ISO
stg
D S
GS
D
D
tot
TYPE
( )
j
Drain-Source Voltage (V
Drain-Gate Voltage (R
Gate-Source Voltage
Drain Current (continuous) at T
Drain Current (continuous) at T
Drain Current (pulsed)
Total Dissipation at T
Derating Factor
Storage Temperature
Max. Operating Junction Temperature
Insulation Withstand Voltage (AC-RMS)
POWER MOS TRANSISTOR IN ISOTOP PACKAGE
500 V
V
DSS
th
JUNCTION TO CASE
< 0.14
Parameter
R
DS( on)
c
GS
= 25
N - CHANNEL ENHANCEMENT MODE
GS
= 20 k )
= 0)
o
C
c
c
36 A
= 25
= 100
I
D
o
C
o
C
INTERNAL SCHEMATIC DIAGRAM
1
-55 to 150
2
Value
2500
ISOTOP
500
500
144
410
150
3.3
36
24
20
STE36N50A
4
3
W/
Unit
o
o
W
V
V
V
A
A
A
V
C
C
o
C
1/8

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STE36N50A Summary of contents

Page 1

... Insulation Withstand Voltage (AC-RMS) ISO ( ) Pulse width limited by safe operating area September 1994 N - CHANNEL ENHANCEMENT MODE INTERNAL SCHEMATIC DIAGRAM = 100 STE36N50A ISOTOP Value Unit 500 V 500 144 A 410 ...

Page 2

... STE36N50A THERMAL DATA R Thermal Resistance Junction-case thj-cas e R Thermal Resistance Case-heatsink With Conductive thc-h Grease Applied AVALANCHE CHARACTERISTICS Symbol I Avalanche Current, Repetitive or Not-Repetitive A R (pulse width limited Single Pulse Avalanche Energy AS o (starting Repetitive Avalanche Energy ...

Page 3

... Test Conditions di/dt = 100 100 150 (see test circuit, figure 3) Thermal Impedance STE36N50A Min. Typ. Max. Unit 120 ns 700 A/ s 295 145 nC Min. Typ. Max. Unit ...

Page 4

... STE36N50A Derating Curve Transfer Characteristics Static Drain-source On Resistance 4/8 Output Characteristics Transconductance Gate Charge vs Gate-source Voltage ...

Page 5

... Capacitance Variations Normalized Breakdown Voltage vs Temperature Turn-on Current Slope Normalized Gate Threshold Voltage vs Temperature Normalized On Resistance vs Temperature Turn-off Drain-source Voltage Slope STE36N50A 5/8 ...

Page 6

... STE36N50A Cross-over Time Fig. 1: Switching Times Test Circuits For Resistive Load Fig. 3: Test Circuit For Inductive Load Switching And Diode Recovery Times 6/8 Source-drain Diode Forward Characteristics Fig. 2: Gate Charge Test Circuit ...

Page 7

... M 37 7 inch MAX. MIN. TYP. 12.2 0.466 9.1 0.350 2.05 0.076 0.85 0.029 12.8 0.496 25.5 0.990 31.7 1.240 0.157 4.3 0.161 15.1 0.586 30.3 1.185 38.2 1.488 0.157 8.2 0.307 0.216 STE36N50A MAX. 0.480 0.358 0.080 0.033 0.503 1.003 1.248 0.169 0.594 1.193 1.503 0.322 0041565 7/8 ...

Page 8

... STE36N50A Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsability for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice ...

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