74HC/HCT190 Philips Semiconductors (Acquired by NXP), 74HC/HCT190 Datasheet
74HC/HCT190
Related parts for 74HC/HCT190
74HC/HCT190 Summary of contents
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... DATA SHEET For a complete data sheet, please also download: The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications The IC06 74HC/HCT/HCU/HCMOS Logic Package Information The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT190 Presettable synchronous BCD decade up/down counter Product specification File under Integrated Circuits, IC06 ...
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... Output capability: standard I category: MSI CC GENERAL DESCRIPTION The 74HC/HCT190 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT190 are asynchronously presettable up/down BCD decade counters. They contain four ...
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... For HCT the condition GND ORDERING INFORMATION See “74HC/HCT/HCU/HCMOS Logic Package Information” December 1990 CONDITIONS pF notes 1 and where 1 Product specification 74HC/HCT190 TYPICAL HC HCT = MHz 3.5 3 UNIT ...
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... LOW) up/down input ground (0 V) parallel load input (active LOW) terminal count output ripple clock output (active LOW) clock input (LOW-to-HIGH, edge-triggered) data inputs positive supply voltage Fig.3 IEC logic symbol. 4 Product specification 74HC/HCT190 Fig.2 Logic symbol. ...
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... TERMINAL COUNT STATE Product specification 74HC/HCT190 OUTPUTS count count down change OUTPUTS ...
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... Philips Semiconductors Presettable synchronous BCD decade up/down counter Fig.6 Synchronous n-stage counter using ripple carry/borrow. Fig.7 Synchronous n-stage counter with parallel gated carry/borrow. December 1990 Fig.5 N-stage ripple counter using ripple clock. 6 Product specification 74HC/HCT190 ...
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... Presettable synchronous BCD decade up/down counter Sequence Load (present) to BCD seven; count up to eight, nine, zero, one and two; inhibit; count down to one, zero, nine, eight and seven. December 1990 Fig.8 Typical load, count and inhibit sequence. Fig.9 Logic diagram. 7 Product specification 74HC/HCT190 ...
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... Product specification 74HC/HCT190 . TEST CONDITIONS UNIT WAVEFORMS 125 (V) min. max. 330 ns 2.0 Fig.10 66 4.5 56 6.0 385 ns 2.0 Fig.10 77 4.5 65 6.0 225 ns 2.0 Fig.11 45 4.5 38 6.0 195 ns 2 ...
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... Product specification 74HC/HCT190 TEST CONDITIONS UNIT WAVEFORMS 125 (V) min. max 2.0 Fig.15 11 4.5 9 6.0 310 ns 2.0 Fig.17 62 4.5 53 6.0 150 ns 2.0 Fig.16 30 4.5 26 6.0 210 ns 2.0 Fig. ...
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... The value of additional quiescent supply current ( I To determine I per input, multiply this value by the unit load coefficient shown in the table below. CC INPUT U/D CE, PL December 1990 ) for a unit load given in the family specifications. CC UNIT LOAD COEFFICIENT 0.5 0.65 1.15 1.5 10 Product specification 74HC/HCT190 . ...
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... Product specification 74HC/HCT190 TEST CONDITIONS UNIT WAVEFORMS 125 (V) min. max 4.5 Fig. 4.5 Fig. 4.5 Fig. 4.5 Fig. 4.5 Fig. 4.5 Fig.13 ...
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... CC HCT : GND Fig.15 Waveforms showing the parallel load input (PL) pulse width, removal time to clock (CP) and the output (Q 12 Product specification 74HC/HCT190 = GND GND GND GND transition times. n ...
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... V = GND HCT : GND Fig.17 Waveforms showing the set-up and hold times from the count enable and up/down inputs (CE, U/D) to the clock (CP). PACKAGE OUTLINES “74HC/HCT/HCU/HCMOS Logic Package Outlines” See December 1990 . 13 Product specification 74HC/HCT190 ). n ...