IDT70V18L15PFI IDT [Integrated Device Technology], IDT70V18L15PFI Datasheet - Page 10

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IDT70V18L15PFI

Manufacturer Part Number
IDT70V18L15PFI
Description
HIGH-SPEED 3.3V 64K x 9 DUAL-PORT STATIC RAM
Manufacturer
IDT [Integrated Device Technology]
Datasheet
NOTES:
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and BUSY (M/S = V
2. To ensure that the earlier of the two ports wins.
3. t
4. To ensure that the write cycle is inhibited on port "B" during contention on port "A".
5. To ensure that a write cycle is completed on port "B" after contention on port "A".
PORT-TO-PORT DELAY TIMING
BUSY TIMING (M/S=V
t
t
t
t
t
t
t
BUSY TIMING (M/S=V
t
t
t
t
BAA
BDA
BAC
BDC
APS
BDD
WH
WB
WH
WDD
DDD
Symbol
IDT70V18L
High-Speed 3.3V 64K x 9 Dual-Port Static RAM
BDD
is a calculated parameter and is the greater of 0, t
BUSY Access Time from Address Match
BUSY Disable Time from Address Not Matched
BUSY Access Time from Chip Enable Low
BUSY Access Time from Chip Enable High
Arbitration Priority Set-up Time
BUSY Disable to Valid Data
Write Hold After BUSY
BUSY Input to Write
Write Hold After BUSY
Write Pulse to Data Delay
Write Data Valid to Read Data Delay
IH
IL
)
)
(4)
(5)
(5)
(1)
(3)
(2)
(1)
WDD
– t
Parameter
WP
(actual), or t
DDD
10
– t
DW
(actual).
Industrial and Commercial Temperature Ranges
Min.
Com'l Only
____
____
____
____
____
____
____
12
12
5
0
70V18L15
Max.
____
____
____
____
30
25
15
15
15
15
15
Min.
____
____
____
____
____
____
____
15
15
5
0
70V18L20
Com'l
& Ind
IH
)".
Preliminary
Max.
____
____
____
____
20
20
20
45
30
17
17
4854 tbl 14
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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