IDT70V18L15PFI IDT [Integrated Device Technology], IDT70V18L15PFI Datasheet - Page 8

• Manufacturer Part Number: IDT70V18L15PFI
• Description: HIGH-SPEED 3.3V 64K x 9 DUAL-PORT STATIC RAM
• Manufacturer: IDT [Integrated Device Technology]

CE or SEM
CE or SEM
NOTES:
1. R/W or CE = V
2. A write occurs during the overlap (t
3. t
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE or SEM = V
6. Timing depends on which enable signal is asserted last, CE or R/W.
7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load
8. If OE = V
9. To access RAM, CE = V
10. Refer to Truth Table I - Chip Enable .
ADDRESS
ADDRESS
DATA
IDT70V18L
High-Speed 3.3V 64K x 9 Dual-Port Static RAM
for the required t
DATA
DATA
WR
(Figure 2).
is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end of write cycle.
R/W
R/ W
OUT
OE
IN
IN
IL
(9,10)
(9,10)
during R/W controlled write cycle, the write pulse width must be the larger of t
IH
DW
during all address transitions.
. If OE = V
IL
transition occurs simultaneously with or after the R/W = V
IL
and SEM = V
IH
during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t
t
EW
AS
t
AS
or t
(6)
IH
WP
. To access semaphore, CE = V
(6)
) of a CE = V
(4)
IL
and a R/W = V
t
WZ
(7)
t
t
AW
AW
t
t
WC
WC
t
t
IH
EW
IL
WP
and SEM = V
for memory array writing cycle.
(2)
(2)
IL
8
transition, the outputs remain in the High-impedance state.
WP
IL
or (t
CE
. t
t
t
EW
DW
DW
WZ
W
must be met for either condition.
+ t
DW
) to allow the I/O drivers to turn off and data to be placed on the bus
Industrial and Commercial Temperature Ranges
t
WR
(3)
t
t
DH
DH
t
WR
t
OW
(3)
t
HZ
(7)
(4)
Preliminary
WP
.
4854 drw 08
4854 drw 07