IDT70V65 IDT [Integrated Device Technology], IDT70V65 Datasheet
IDT70V65
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IDT70V65 Summary of contents
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... Commercial: 10/12/15ns (max.) – Industrial: 12/15ns (max.) Dual chip enables allow for depth expansion without external logic IDT70V659/58/57 easily expands data bus width to 72 bits or more using the Master/Slave select when cascading more than one device M for BUSY output flag on Master, ...
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... High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM Description The IDT70V659/58/ high-speed 128/64/32K x 36 Asynchro- nous Dual-Port Static RAM. The IDT70V659/58/57 is designed to be used as a stand-alone 4/2/1Mbit Dual-Port RAM combination MASTER/ SLAVE Dual-Port RAM for 72-bit-or-more word system. Using the IDT ...
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... I/O 33L 51 I/O 34R I/O 52 34L NOTES: 1. Pin for IDT70V658 and IDT70V657. 2. Pin for IDT70V657. 3. All V pins must be connected to 3.3V power supply All V pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to V DDQ set to V (0V All V pins must be connected to ground ...
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... TCK NOTES: 1. Pin for IDT70V658 and IDT70V657. 2. Pin for IDT70V657. 3. All V pins must be connected to 3.3V power supply All V pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to V DDQ set to V (0V). ...
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... DDQL I 35L NOTES: 1. Pin for IDT70V658 and IDT70V657. 2. Pin for IDT70V657. 3. All V pins must be connected to 3.3V power supply All V pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to V DDQ set to V (0V). ...
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... I/Os and controls will operate at 2.5V levels and V at 2.5V. The OPT pins are independent of one another—both ports can operate at 3.3V levels, both can operate at 2.5V levels, or either can operate at 3.3V with the other at 2.5V. 3. Addresses for IDT70V658. Also, Addresses A 16 4869 tbl 01 NC's for IDT70V657. 4. BUSY is an input as a slave (M ...
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... IDT70V659/58/57S High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM Truth Table I—Read/Write and Enable Control CE OE SEM ...
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... IDT70V659/58/57S High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM Recommended DC Operating Conditions with V DDQ Symbol Parameter Min. V Core Supply Voltage 3.15 DD (3) V I/O Supply Voltage 2.4 DDQ V Ground 0 SS (3) Input High Voltage 1 (Address & Control Inputs) (3) V Input High Voltage - I/O 1.7 IH (1) V Input Low Voltage -0 ...
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... IDT70V659/58/57S High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Symbol Parameter ( Input Leakage Current Output Leakage Current LO (2) V (3.3V) Output Low Voltage OL (2) V (3.3V) Output High Voltage OH (2) V (2.5V) Output Low Voltage ...
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... IDT70V659/58/57S High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM AC Test Conditions (V Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load 50Ω DATA OUT Figure 1. AC Output Test load tAA (Typical, ns ...
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... IDT70V659/58/57S High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Symbol READ CYCLE t Read Cycle Time RC t Address Access Time AA (3) t Chip Enable Access Time ACE (3) t Byte Enable Access Time ...
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... IDT70V659/58/57S High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM Waveform of Read Cycles ADDR ( BEn R/W DATA OUT BUSY OUT NOTES: 1. Timing depends on which signal is asserted last, OE BEn. 2. Timing depends on which signal is de-asserted first CE BEn delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY BDD has no relation to valid output data ...
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... IDT70V659/58/57S High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM Timing Waveform of Write Cycle No. 1, R/W Controlled Timing ADDRESS OE ( SEM (9) BEn ( R/W DATA OUT DATA IN Timing Waveform of Write Cycle No Controlled Timing ADDRESS ( SEM ( (9) BEn R/W DATA IN NOTES: 1 ...
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... IDT70V659/58/57S High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM Timing Waveform of Semaphore Read after Write Timing, Either Side VALID ADDRESS t SEM/BEn (1) I R/W OE NOTES for the duration of the above timing (both write and read cycle) (Refer to Chip Enable Truth Table). Refer also to Truth Table II for appropriate BE controls. ...
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... IDT70V659/58/57S High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Symbol BUSY TIMING (M/S BUSY Access Time from Address Match BAA t BUSY Disable Time from Address Not Matched BDA t BUSY Access Time from Chip Enable Low ...
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... IDT70V659/58/57S High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM Timing Waveform of Write with Port-to-Port Read and BUSY (M ADDR "A" R/W "A" DATA IN "A" (1) t APS ADDR "B" BUSY "B" DATA OUT "B" NOTES ensure that the earlier of the two ports wins ...
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... IDT70V659/58/57S High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM Waveform of BUSY Arbitration Controlled by CE Timing (M ADDR "A" and "B" CE "A" (2) t APS CE "B" BUSY "B" Waveform of BUSY Arbitration Cycle Controlled by Address Match Timing (M (1) IH ADDR " ...
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... V , then no change INT and INT must be initialized at power-up for IDT70V658, therefore Interrupt Addresses are FFFF and FFFE and A x are NC's for IDT70V657, therefore Interrupt Addresses are 7FFF and 7FFE ( INTERRUPT SET ADDRESS ...
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... Right Port Writes "1" to Semaphore Left Port Writes "0" to Semaphore Left Port Writes "1" to Semaphore NOTES: 1. This table denotes a sequence of events for only one of the eight semaphores on the IDT70V659/58/57. 2. There are eight semaphore flags written to via I SEM = V to access the semaphores ...
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... BUSY indication, and to output that indication. Any ) is asserted when number of slaves to be addressed in the same address range as the master R use the BUSY signal as a write inhibit signal. Thus on the IDT70V659/58/ ), the right 57 RAM the BUSY pin is an output if the part is used as a master (M/S pin R ...
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... The eight semaphore flags reside within the IDT70V659/58/ separate memory space from the Dual-Port RAM. This address space is accessed by placing a low input on the SEM pin (which acts as a chip select for the semaphore flags) and using the other control pins (Address, CE, R/W and BEo) as they would be used in accessing a standard Static RAM ...
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... IDT70V659/58/57S High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM JTAG Timing Specifications t JF TCK (1) Device Inputs / TDI/TMS (2) Device Outputs / TDO TRST t JRST NOTES: 1. Device inputs = All device inputs except TDI, TMS, and TRST. 2. Device outputs = All device outputs except TDO. ...
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... Identification Register Definitions Instruction Field Revision Number (31:28) IDT Device ID (27:12) IDT JEDEC ID (11:1) ID Register Indicator Bit (Bit 0) NOTE: 1. Device ID for IDT70V658 is 0x30B. Device ID for IDT70V657 is 0x323. Scan Register Sizes Register Name Instruction (IR) Bypass (BYR) Identification (IDR) Boundary Scan (BSR) System Interface Parameters ...
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... IDT70V659/58/57S High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM Ordering Information IDT XXXXX A 999 Device Power Speed Package Type NOTE: 1. Contact your local sales office for industrial temp range for other speeds, packages and powers. Datasheet Document History: 6/2/00: Initial Public Offering 8/11/00: Page 6, 13 & ...