SST25LF080A-33-4C-S2AE SST [Silicon Storage Technology, Inc], SST25LF080A-33-4C-S2AE Datasheet
SST25LF080A-33-4C-S2AE
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SST25LF080A-33-4C-S2AE Summary of contents
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... The SST25LF080A devices operate with a single 3.0-3.6V power supply. The SST25LF080A devices are offered in an 8-lead SOIC package with 200 mil body width. See Figure 1 for pin assignments. The SST logo and SuperFlash are registered Trademarks of Silicon Storage Technology, Inc. ...
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... EOL Product Data Sheet UNCTIONAL LOCK IAGRAM Address Buffers and Latches CE# ©2006 Silicon Storage Technology, Inc Decoder Control Logic Serial Interface SCK SI SO WP# HOLD Mbit SPI Serial Flash SST25LF080A SuperFlash Memory Y - Decoder I/O Buffers and Data Latches 1248 B1.0 S71248-06-EOL 1/06 ...
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... The Write Protect (WP#) pin is used to enable/disable BPL bit in the status register. HOLD# Hold To temporarily stop serial communication with SPI flash memory without resetting the device. V Power Supply To provide power supply voltage: 3.0-3.6V for SST25LF080A DD V Ground SS ©2006 Silicon Storage Technology, Inc. CE# ...
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... BFH Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK). 80H The SST25LF080A supports both Mode 0 (0,0) and Mode T2.0 1248 3 (1,1) of SPI bus operations. The difference between the two modes, as shown in Figure 2, is the state of the SCK signal when the bus master is in Stand-by mode and no data is being transferred ...
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... W OLD ONDITION Write Protection SST25LF080A provides software Write protection. The Write Protect pin (WP#) enables or disables the lock-down function of the status register. The Block-Protection bits (BP1, BP0, and BPL) in the status register provide Write protection to the memory array and the status register. See Table 5 for Block-Protection description ...
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... Silicon Storage Technology, Inc. 8 Mbit SPI Serial Flash Program operation, the status register may be read only to determine the completion of an operation in progress. Table 4 describes the function of each bit in the software status register. Default at Power- SST25LF080A Read/Write R R R/W R/W N/A R R/W T4.0 1248 S71248-06-EOL 1/06 ...
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... Mbit SPI Serial Flash SST25LF080A Block Protection (BP1, BP0) The Block-Protection (BP1, BP0) bits define the size of the memory area, as defined in Table software pro- tected against any memory Write (Program or Erase) operations. The Write-Status-Register (WRSR) instruction is used to program the BP1 and BP0 bits as long as WP# is high or the Block-Protect-Lock (BPL) bit is 0 ...
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... EOL Product Data Sheet Instructions Instructions are used to Read, Write (Erase and Program), and configure the SST25LF080A. The instruction bus cycles are 8 bits each for commands (Op Code), data, and addresses. Prior to executing any Byte-Program, Auto Address Increment (AAI) programming, Sector-Erase, Block-Erase, or Chip-Erase instructions, the Write-Enable (WREN) instruction must be executed first ...
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... Mbit SPI Serial Flash SST25LF080A Read (20 MHz) The Read instruction supports MHz, it outputs the data starting from the specified address location. The data output stream is continuous through all addresses until ter- minated by a low to high transition on CE#. The internal address pointer will automatically increment until the high- est memory address is reached ...
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... ADD. ADD. ADD. X MSB MSB EQUENCE 10 8 Mbit SPI Serial Flash SST25LF080A N+1 N+2 N+3 N OUT OUT OUT OUT OUT 1248 F05 ...
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... Mbit SPI Serial Flash SST25LF080A Byte-Program The Byte-Program instruction programs the bits in the selected byte to the desired data. The selected byte must be in the erased state (FFH) when initiating a Program operation. A Byte-Program instruction applied to a pro- tected memory area will be ignored. ...
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... Write Disable (WRDI) Instruction to terminate AAI Operation (AAI ROGRAM EQUENCE 12 8 Mbit SPI Serial Flash SST25LF080A for the completion of each inter Data Byte 2 05 Read Status Register (RDSR) Instruction to verify end of AAI Operation ...
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... Mbit SPI Serial Flash SST25LF080A Sector-Erase The Sector-Erase instruction clears all bits in the selected 4 KByte sector to FFH. A Sector-Erase instruction applied to a protected memory area will be ignored. Prior to any Write operation, the Write-Enable (WREN) instruction must be executed. CE# must remain active low for the duration of the any command sequence ...
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... CE#. See Figure 11 for the RDSR instruction sequence Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MSB (RDSR) S EQUENCE 14 8 Mbit SPI Serial Flash SST25LF080A Status 1248 F11.0 Register Out S71248-06-EOL for CE 1/06 ...
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... Mbit SPI Serial Flash SST25LF080A Write-Enable (WREN) The Write-Enable (WREN) instruction sets the Write- Enable-Latch bit to 1 allowing Write operations to occur. The WREN instruction must be executed prior to any Write (Program/Erase) operation. CE# must be driven high before the WREN instruction is executed. FIGURE 12 ...
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... MODE 3 MODE 0 01 MSB HIGH IMPEDANCE -R (EWSR EGISTER AND RITE TATUS 16 8 Mbit SPI Serial Flash SST25LF080A ) prior to the low-to-high transi- IH STATUS REGISTER MSB 1248 F14.0 -R (WRSR) S EGISTER EQUENCE S71248-06-EOL 1/06 ...
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... Mbit SPI Serial Flash SST25LF080A Read-ID The Read-ID instruction identifies the devices as SST25LF080A and manufacturer as SST. The device information can be read from executing an 8-bit command, 90H or ABH, followed by address bits [A the Read-ID instruction, the manufacturer’ located in CE# MODE ...
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... V OUT OWER UP IMINGS 18 8 Mbit SPI Serial Flash SST25LF080A EST = /0.9 V @20 MHz, SO=open DD DD /0.9 V @33 MHz, SO=open =GND Max =GND ...
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... Mbit SPI Serial Flash SST25LF080A TABLE 9: C APACITANCE (Ta = 25°C, f=1 Mhz, other pins open) Parameter Description 1 C Output Pin Capacitance OUT 1 C Input Capacitance IN 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. ...
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... CLZ SO SI FIGURE 17 ERIAL UTPUT IMING ©2006 Silicon Storage Technology, Inc. T SCKF T SCKR D IAGRAM T SCKL T OH MSB IAGRAM 20 8 Mbit SPI Serial Flash SST25LF080A T CPH T T CEH CHS LSB HIGH-Z 1248 F16.0 T CHZ LSB 1248 F17.0 S71248-06-EOL 1/06 ...
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... Mbit SPI Serial Flash SST25LF080A CE# SCK SO SI HOLD# FIGURE 18 OLD IMING IAGRAM Max DD Chip selection is not allowed. Commands may not be accepted or properly interpreted by the device. V Min DD FIGURE 19 OWER UP IMING ©2006 Silicon Storage Technology, Inc HHH HLS ...
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... V (0.3V ). Input rise and fall times (10 EFERENCE AVEFORMS TO TESTER TO DUT 1248 F21 Mbit SPI Serial Flash SST25LF080A V HT OUTPUT V LT 1248 F20.0 ) for a logic “0”. Measurement reference points ↔ 90%) are <5 ns. Note Test HT HIGH Test ...
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... XX XX XXXX X - XXX Valid combinations for SST25LF080A SST25LF080A-33-4C-S2AE SST25LF080A-33-4I-S2AE SST25LF080A-33-4E-S2AE Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations. ©2006 Silicon Storage Technology, Inc. ...
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... LEAD MALL UTLINE NTEGRATED SST S2A ACKAGE ODE ©2006 Silicon Storage Technology, Inc. SIDE VIEW 0.50 0.35 1.27 BSC 0.25 0.05 2.16 1.75 0.25 0.19 C (SOIC) 200 IRCUIT MIL BODY WIDTH 24 8 Mbit SPI Serial Flash SST25LF080A END VIEW 0.80 0.50 08-soic-EIAJ-S2A-3 1mm (5 S71248-06-EOL 0˚ 8˚ 1/06 ...
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... Mbit SPI Serial Flash SST25LF080A TABLE 12 EVISION ISTORY Number 00 • Initial release of data sheet 01 • 2004 Data Book 02 • Changes to Table 7 on page 18 – Added I DDR1 – Changed I to from DDR • Clarified comments in Figure 19 on page 21 • ...