SST45LF010-10-4C-SA SST [Silicon Storage Technology, Inc], SST45LF010-10-4C-SA Datasheet

SST45LF010-10-4C-SA

Manufacturer Part Number

SST45LF010-10-4C-SA

Description

1 Megabit Serial Flash

Manufacturer

SST [Silicon Storage Technology, Inc]

Datasheet

1.SST45LF010-10-4C-SA.pdf (14 pages)

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FEATURES:

• Single 3.0-3.6V Read and Write Operations

• Serial Interface Architecture

• Byte Serial Read with Single Command

• Superior Reliability

• Low Power Consumption

• Sector or Chip-Erase Capability

• Fast Erase and Byte-Program

PRODUCT DESCRIPTION

The SST45LF010 is a 1 Mbit serial flash memory manufac-

tured with SST’s proprietary, high performance CMOS

SuperFlash technology. The 1 Mbit of memory is organized

as 32 sectors of 4096 Bytes. The flash memory uses a 3-

wire serial interface and a chip enable to select and

sequentially access its data. The serial interface consists

of; serial data input (SI), serial data output (SO), serial clock

(SCK), and chip enable (CE#). A write protect (WP#) inhib-

its the entire memory from write operation and a hardware

reset pin (RST#) resets the device to standby mode.

The SST45LF010 device is offered in both 8-lead SOIC

and 8-contact WSON packages. See Figure 1 for the

pinouts.

Device Operation

The SST45LF010 uses bus cycles of 8 bits each for com-

mands, data, and addresses to execute operations. The

operation instructions are listed in Table 3.

All instructions are synchronized off a high to low transition

of CE#. The first low to high transition on SCK will initiate

the instruction sequence. Inputs will be accepted on the ris-

ing edge of SCK starting with the most significant bit. Any

low to high transition on CE# before the input instruction

completes will terminate any instruction in progress and

return the device to the standby mode.

S71128-03-000 4/01

– Endurance: 100,000 Cycles (typical)

– Greater than 100 years Data Retention

– Active Current: 10 mA (typical)

– Standby Current: 10 µA (typical)

– Uniform 4 KByte sectors

– Chip-Erase Time: 70 ms (typical)

– Sector-Erase Time: 18 ms (typical)

– Byte-Program Time: 14 µs (typical)

372

SST45LF0101Mb Serial Architecture Interface flash memory

1 Megabit Serial Flash

SST45LF010

The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.

• Automatic Write Timing

• End-of-Write Detection

• 10 MHz Max Clock Frequency

• Hardware Reset Pin (RST#)

• CMOS I/O Compatibility

• Hardware Data Protection (WP#)

• Packages Available

Read

The Read operation outputs the data in order from the ini-

tial accessed address. While SCK is input, the address will

be incremented automatically until end (top) of the address

space (1FFFFH), then the internal address pointer auto-

matically increments to beginning (bottom) of the address

space (00000H), and data out stream will continue. The

read data stream is continuous through all addresses until

terminated by a low to high transition on CE#.

Sector/Chip-Erase Operation

The Sector-Erase operation clears all bits in the selected

sector to FFH. The Chip-Erase instruction clears all bits in

the device to FFH.

Byte-Program Operation

The Byte-Program operation programs the bits in the

selected byte to the desired data. The selected byte must

be in the erased state (FFH) when initiating a Program

operation. The data is input from bit 7 to bit 0 in order.

Software Status Operation

The Status operation determines if an Erase or Program

operation is in progress. If bit 0 is at a “0” an Erase or Pro-

gram operation is in progress, the device is busy. If bit 0 is

at a “1” the device is ready for any valid operation. The sta-

tus read is continuous with ongoing clock cycles until termi-

nated by a low to high transition on CE#.

– Internal V

– Software Status

– Resets the device to Standby Mode

– Protects and unprotects the device from Write

– 8-lead SOIC (4.9mm x 6mm)

– 8-contact WSON

operation

Generation

These specifications are subject to change without notice.

Data Sheet

Related parts for SST45LF010-10-4C-SA

SST45LF010-10-4C-SA Summary of contents

Page 1

... WSON packages. See Figure 1 for the pinouts. Device Operation The SST45LF010 uses bus cycles of 8 bits each for com- mands, data, and addresses to execute operations. The operation instructions are listed in Table 3. All instructions are synchronized off a high to low transition of CE# ...

Page 2

... The WP# pin has an internal pull-up and could remain unconnected when not used Decoder Control Logic Serial Interface CE# SCK Megabit Serial Flash SST45LF010 Data Sheet I RODUCT DENTIFICATION Byte 0000H 0001H with a stan- SS with a pull-up resistor, then all operations may DD SuperFlash ...

Page 3

... Megabit Serial Flash SST45LF010 Data Sheet 1 WP Top View CE SCK 8- SOIC LEAD FIGURE SSIGNMENTS TABLE ESCRIPTION Symbol Pin Name Functions SCK Serial Clock To provide the timing of the serial interface. Commands, addresses, or input data are latched on the rising edge of the clock input, while output data is shifted out on the falling edge of the clock input ...

Page 4

... Byte-Program 10H Hi Status Reg. 9FH X X Read-ID 90H Hi-Z 00H 1. For SST45LF010 are “Don’t Care.” One bus cycle is eight clock periods 3. Operation: S =Serial In, S =Serial Out IN OUT 4. X=Dummy cycles (Don’t Care are used to determine sector address, A ...

Page 5

... Megabit Serial Flash SST45LF010 Data Sheet Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55° ...

Page 6

... 3.0-3.6V DD Min 45 45 250 250 250 Megabit Serial Flash SST45LF010 Data Sheet Maximum OUT T6.1 372 Units Test Method JEDEC Standard A117 Years JEDEC Standard A103 mA JEDEC Standard 78 T7.1 372 Limits Max ...

Page 7

... Megabit Serial Flash SST45LF010 Data Sheet V IHT INPUT V ILT AC test inputs are driven at V (0.9 V IHT for inputs and outputs are V (0 FIGURE NPUT UTPUT TO DUT FIGURE EST OAD XAMPLE ©2001 Silicon Storage Technology, Inc REFERENCE POINTS ) for a logic “ ...

Page 8

... T SCKL IAGRAM NACTIVE ERIAL LOCK T OH DATA VALID IAGRAM NACTIVE ERIAL LOCK 8 1 Megabit Serial Flash SST45LF010 Data Sheet T CPH T CEH HIGH-Z 372 ILL F04 CEH T CHZ 372 ILL F05 S71128-03-000 4/01 372 ...

Page 9

Page 10

... ADD. ADD. ADD. Din MSB HIGH IMPEDANCE D IAGRAM ADD. ADD. X ADD. HIGH IMPEDANCE 10 1 Megabit Serial Flash SST45LF010 Data Sheet T WPH SELF-TIMED BYTE- PROGRAM CYCLE X LSB 372 ILL F08 N+1 N+2 Dout ...

Page 11

... Megabit Serial Flash SST45LF010 Data Sheet WP# CE SCK 90H SI SO Note: 1. SST Manufacturer BFH is read with SST45LF010 Device ID = 42H is read with FIGURE 10 EAD IMING WP# CE SCK SI HIGH IMPEDANCE SO FIGURE 11: S ...

Page 12

... NACTIVE LOCK OLARITY T PURST T REC T D IMING IAGRAM D IAGRAM 12 1 Megabit Serial Flash SST45LF010 Data Sheet T REC T CES T RST T RLZ HIGH IMPEDANCE 372 ILL F20 372 ILL F13.3 T WPH T CPH T CEH 372 ILL F14.1 S71128-03-000 4/01 372 ...

Page 13

... Speed Suffix1 SST45LFxxx - XXX - XX SST45LF010 Valid combinations SST45LF010-10-4C-SA SST45LF010-10-4C-QA Example: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations. ©2001 Silicon Storage Technology, Inc. Suffix2 ...

Page 14

... Side View .19 .25 5.00 BSC .076 .05 Max .70 .80 8-wson-5x6-QA-ILL (WSON) UTLINE O LEAD ACKAGE www.SuperFlash.com or www.ssti.com 14 1 Megabit Serial Flash SST45LF010 Data Sheet .51 .33 End View 45˚ 7˚ 4 places 1.27 0.40 08.soic-SA-ILL.5 Bottom View Pin #1 4.00 3.40 .50 .75 Cross Section S71128-03-000 4/01 0˚ 8˚ ...

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