IDT82V3380AEQGBLANK IDT [Integrated Device Technology], IDT82V3380AEQGBLANK Datasheet - Page 151

• Manufacturer Part Number: IDT82V3380AEQGBLANK
• Manufacturer: IDT [Integrated Device Technology]

7.2.10
SYNC_MONITOR_CNFG - Sync Monitor Configuration
SYNC_PHASE_CNFG - Sync Phase Configuration
Programming Information
IDT82V3380A
Address:7CH
Type: Read / Write
Default Value: X0101011
Address:7DH
Type: Read / Write
Default Value: XXXXXX00
6 - 4
3 - 0
7 - 2
1 - 0
Bit
Bit
7
7
-
7
-
SYNCHRONIZATION CONFIGURATION REGISTERS
SYNC_MON_LIMT[2:0]
SYNC_PH1[1:0]
SYNC_MON_LIMT2
Name
Name
-
-
-
6
-
6
Reserved.
These bits set the sampling of EX_SYNC1 when EX_SYNC1 is enabled to synchronize the frame sync output signal. Nomi-
nally, the falling edge of EX_SYNC1 is aligned with the rising edge of the T0 selected input clock.
00: On target. (default)
01: 0.5 UI early.
10: 1 UI late.
11: 0.5 UI late.
Reserved.
These bits set the limit for the external sync alarm.
000: ±1 UI.
001: ±2 UI.
010: ±3 UI. (default)
011: ±4 UI.
100: ±5 UI.
101: ±6 UI.
110: ±7 UI.
111: ±8 UI.
These bits must be set to ‘1011’.
SYNC_MON_LIMT1
5
-
5
4
-
SYNC_MON_LIMT0
151
4
3
-
Description
Description
3
-
2
-
SYNCHRONOUS ETHERNET WAN PLL™
2
-
SYNC_PH11
1
1
-
SYNC_PH10
May 16, 2011
0
0
-