IDT82V3380AEQGBLANK IDT [Integrated Device Technology], IDT82V3380AEQGBLANK Datasheet - Page 6

• Manufacturer Part Number: IDT82V3380AEQGBLANK
• Manufacturer: IDT [Integrated Device Technology]

List of Tables
Table 1: Pin Description ............................................................................................................................................................................................. 13
Table 2: Related Bit / Register in Chapter 3.2 ........................................................................................................................................................... 19
Table 3: Related Bit / Register in Chapter 3.3 ........................................................................................................................................................... 20
Table 4: Pre-Divider Function .................................................................................................................................................................................... 22
Table 5: Related Bit / Register in Chapter 3.4 ........................................................................................................................................................... 22
Table 6: Related Bit / Register in Chapter 3.5 ........................................................................................................................................................... 24
Table 7: Input Clock Selection for T0 Path ................................................................................................................................................................ 25
Table 8: Input Clock Selection for T4 Path ................................................................................................................................................................ 25
Table 9: External Fast Selection ................................................................................................................................................................................ 25
Table 10: Related Bit / Register in Chapter 3.6 ........................................................................................................................................................... 26
Table 11: Coarse Phase Limit Programming (the selected input clock of 2 kHz, 4 kHz or 8 kHz) .............................................................................. 27
Table 12: Coarse Phase Limit Programming (the selected input clock of other than 2 kHz, 4 kHz and 8 kHz) .......................................................... 27
Table 13: Related Bit / Register in Chapter 3.7 ........................................................................................................................................................... 28
Table 14: Conditions of Qualified Input Clocks Available for T0 & T4 Selection ......................................................................................................... 29
Table 15: Related Bit / Register in Chapter 3.8 ........................................................................................................................................................... 30
Table 16: T0 DPLL Operating Mode Control ............................................................................................................................................................... 31
Table 17: T4 DPLL Operating Mode Control ............................................................................................................................................................... 33
Table 18: Related Bit / Register in Chapter 3.9 ........................................................................................................................................................... 33
Table 19: Frequency Offset Control in Temp-Holdover Mode ..................................................................................................................................... 34
Table 20: Frequency Offset Control in Holdover Mode ............................................................................................................................................... 35
Table 21: Holdover Frequency Offset Read ................................................................................................................................................................ 35
Table 22: Related Bit / Register in Chapter 3.10 ......................................................................................................................................................... 36
Table 23: Related Bit / Register in Chapter 3.11 ......................................................................................................................................................... 38
Table 24: Related Bit / Register in Chapter 3.12 ......................................................................................................................................................... 39
Table 25: Outputs on OUT1 ~ OUT7 if Derived from T0/T4 DPLL Outputs ................................................................................................................ 40
Table 26: Outputs on OUT1 ~ OUT7 if Derived from T0 APLL ................................................................................................................................... 41
Table 27: Outputs on OUT1 & 2 & 4 & 5 & 6 if Derived from T4 APLL ........................................................................................................................ 42
Table 28: Outputs on OUT3 & OUT7 if Derived from T4 APLL ................................................................................................................................... 43
Table 29: Outputs on OUT8 & OUT9 ........................................................................................................................................................................... 43
Table 30: Synchronization Control ............................................................................................................................................................................... 44
Table 31: Related Bit / Register in Chapter 3.13 ......................................................................................................................................................... 46
Table 32: Device Master / Slave Control ..................................................................................................................................................................... 47
Table 33: Related Bit / Register in Chapter 3.15 ......................................................................................................................................................... 48
Table 34: Microprocessor Interface ............................................................................................................................................................................. 51
Table 35: Microprocessor Interface Pins ..................................................................................................................................................................... 51
Table 36: Access Timing Characteristics in EPROM Mode ......................................................................................................................................... 52
Table 37: Read Timing Characteristics in Multiplexed Mode ....................................................................................................................................... 53
Table 38: Write Timing Characteristics in Multiplexed Mode ....................................................................................................................................... 54
Table 39: Read Timing Characteristics in Intel Mode .................................................................................................................................................. 55
Table 40: Write Timing Characteristics in Intel Mode .................................................................................................................................................. 56
Table 41: Read Timing Characteristics in Motorola Mode ........................................................................................................................................... 57
Table 42: Write Timing Characteristics in Motorola Mode ........................................................................................................................................... 58
Table 43: Read Timing Characteristics in Serial Mode ................................................................................................................................................ 59
Table 44: Write Timing Characteristics in Serial Mode ................................................................................................................................................ 60
Table 45: JTAG Timing Characteristics ....................................................................................................................................................................... 61
Table 46: Register List and Map .................................................................................................................................................................................. 62
Table 47: Power Consumption and Maximum Junction Temperature ....................................................................................................................... 152
Table 48: Thermal Data ............................................................................................................................................................................................. 152
List of Tables
6
May 16, 2011