IDT82V3380AEQGBLANK IDT [Integrated Device Technology], IDT82V3380AEQGBLANK Datasheet - Page 54

• Manufacturer Part Number: IDT82V3380AEQGBLANK
• Manufacturer: IDT [Integrated Device Technology]

Table 38: Write Timing Characteristics in Multiplexed Mode
Microprocessor Interface
IDT82V3380A
Symbol
t
t
t
t
t
t
t
t
t
t
pw1
pw2
pw3
t
t
t
t
t
su1
su2
su3
t
out
t
T
d2
d5
d6
h1
h2
h3
h4
TI
in
T
AD[7:0]
Time between consecutive Write-Read or Write-Write accesses
WR
RDY
ALE
RD
CS
Time between ALE falling edge and WR falling edge
Valid address after ALE falling edge hold time
Valid address to ALE falling edge setup time
CS rising edge to RDY release delay time
Valid WR after RDY rising edge hold time
Valid data after WR rising edge hold time
Valid data to WR rising edge setup time
Valid CS after WR rising edge hold time
WR rising edge to RDY low delay time
(WR rising edge to ALE rising edge)
One cycle time of the master clock
Valid CS to valid RDY delay time
Valid CS to valid WR setup time
High-Z
Valid ALE pulse width high
Valid RDY pulse width low
t
Valid WR pulse width low
pw3
t
su1
address
Delay of output pad
Delay of input pad
Figure 20. Multiplexed Write Timing Diagram
Parameter
t
h1
t
d2
t
T
t
su2
54
t
pw2
t
pw1
t
su3
data
1.5T + 10
1.5T + 10
t
h3
Min
>7T
2
0
3
2
3
0
0
9
0
SYNCHRONOUS ETHERNET WAN PLL™
t
h4
t
h2
t
d5
12.86
Typ
13
13
13
5
5
t
d6
High-Z
Max
May 16, 2011
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns