IDT82V3380AEQGBLANK IDT [Integrated Device Technology], IDT82V3380AEQGBLANK Datasheet - Page 77

• Manufacturer Part Number: IDT82V3380AEQGBLANK
• Manufacturer: IDT [Integrated Device Technology]

7.2.2
INTERRUPT_CNFG - Interrupt Configuration
INTERRUPTS1_STS - Interrupt Status 1
Programming Information
IDT82V3380A
Address: 0CH
Type: Read / Write
Default Value: XXXXXX10
Address: 0DH
Type: Read / Write
Default Value: 11111111
7 - 2
7 - 0
Bit
Bit
1
0
IN8
7
7
-
INTERRUPT REGISTERS
INT_POL
HZ_EN
Name
Name
INn
-
IN7
6
6
-
Reserved.
This bit determines the output characteristics of the INT_REQ pin.
0: The output on the INT_REQ pin is high/low when the interrupt is active; the output is the opposite when the interrupt is inactive.
1: The output on the INT_REQ pin is high/low when the interrupt is active; the output is in high impedance state when the interrupt
is inactive. (default)
This bit determines the active level on the INT_REQ pin for an active interrupt indication.
0: Active low. (default)
1: Active high.
This bit indicates the validity changes (from ‘valid’ to ‘invalid’ or from ‘invalid’ to ‘valid’) for the corresponding INn; i.e., whether
there is a transition (from ‘0’ to ‘1’ or from ‘1’ to ‘0’) on the corresponding INn bit (b7~0, 4AH). Here n is any one of 8 to 1.
0: Has not changed.
1: Has changed. (default)
This bit is cleared by writing a ‘1’.
IN6
5
-
5
IN5
4
-
4
77
IN4
3
-
3
Description
Description
IN3
2
-
2
SYNCHRONOUS ETHERNET WAN PLL™
HZ_EN
IN2
1
1
INT_POL
May 16, 2011
IN1
0
0