FS401LF ETC2 [List of Unclassifed Manufacturers], FS401LF Datasheet

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FS401LF

Manufacturer Part Number
FS401LF
Description
PC to TV Video Scan Converters
Manufacturer
ETC2 [List of Unclassifed Manufacturers]
Datasheet

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Part Number
Manufacturer
Quantity
Price
Part Number:
FS401LF
Manufacturer:
FOUCS
Quantity:
8 500
JANUARY 24, 2007
–Minimum 640x 400
–Maximum 2048 x 1536
–XGA and above
–NTSC, NTSC-EIAJ, PAL-B/G/H/I †
–Composite, S-Video, SCART
–RGB, YUV
Standard NTSC and PAL
Super NTSC & PAL
VGA Progressive
SVGA Progressive
NTSC Progressive
PAL 100Hz Interlaced
Features
Frame rate Conversion †
Programmable 2D scaling †
Pan and Zoom †
Advanced 2-D flicker filter †
Frame-store memory controller
Supports Multiple Progressive Input
Resolutions †
Supports Interlaced Input
Input refresh rates up to 150Hz
Multiple Output Standards
Automatically detects input active video
area
Automatically selects the best output and
scaling for any input resolution
Programmable sharpness, brightness,
contrast and color saturation
Customizable On Screen Display via
glueless integration with Zilog and Philips
OSD Microprocessors (FS403)
C, H, and V Sync tri-state outputs
H and V Sync monitoring for DPMS
Support
Exceeds all PC97 and PC98 requirements
General Purpose Output Pins
(2 on FS401, 7 on FS403)
Genlock (FS403)
8-bit A/D converters with frequency
adaptive input filtering support
10-bit output D/A converters
Digital RGB Inputs (FS403)
I
100 pin PQFP (FS401)
128 pin PQFP (FS403)
3.3V operation
RoHS Compliant
2
C
compatible port controls (SIO)
COPYRIGHT ©1999, 2000, 2003 FOCUS ENHANCEMENTS, INC.
1
†Note: Covered under US Patent # 5,862,268, #
5,905,536, # 5,966,184 and/or patents pending.
Description
The FS400 family is a fourth generation
video scan converter. It accepts many
input resolutions and rates and converts
them to NTSC or PAL standards compliant
with SMPTE-170M and CCIR-656
standards. Also available as output
options are VGA 640 x 480 at 60Hz
progressive, SVGA 800 x 600 at 60Hz
progressive, and 100 Hz interlaced. The
chip has a programmable down scaler to fit
the incoming resolution to the output
display format. Within the FS400 are
capture and encoder engines separated by
the frame buffer memory controller.
Required external components are
minimal: a single 16M SDRAM memory,
clocks and passive parts.
Analog progressive RGB inputs are
digitized and converted to the YUV 4:2:2
format. Vertical scaling and flicker filtering
are implemented at the computer frame
rate ahead of the frame store interface.
Interlaced input is supported for XGA
resolution and above. In this mode, only
the first field is processed.
The Flicker Filter is an advanced 2
dimensional filter that enhances text
quality. Flicker Filter parameters are
programmable to allow user tradeoffs
between flicker and sharpness.
The FS400 family contains controls for
programmable sharpness, brightness,
contrast, and color saturation. These
controls allow output to be tuned to match
user desires and tastes.
Frame rate conversion is
implemented by a Frame Store
Controller that interfaces with an
external SDRAM frame store
memory.
YUV 4:2:2 data is recovered from
the memory at the outgoing frame
rate. Data is scaled prior to the
Scan Converters
PC to TV Video
FS401, FS403

Related parts for FS401LF

FS401LF Summary of contents

Page 1

Features • Frame rate Conversion † • Programmable 2D scaling † • Pan and Zoom † • Advanced 2-D flicker filter † • Frame-store memory controller • Supports Multiple Progressive Input Resolutions † –Minimum 640x 400 –Maximum 2048 x 1536 ...

Page 2

FS401, FS403 digital video encoder that generates Y/C and Composite Video outputs. For RGB and YUV outputs, the encoder may be bypassed via a YUV to RGB transcoder for SCART compatible video, and for output to VGA or SVGA displays. ...

Page 3

FS401, FS403 Contents 1. Architectural Overview .................................... 5 1.1 Video Capture Engine............................. 5 1.2 Frame Store Memory Controller ............. 6 1.3 Video Encoder Engine ............................ 6 1.4 Serial Control Port .................................. 6 1.5 Typical System Configurations ............... 7 1.5.1 External ...

Page 4

... Interfacing to the FS400 in a Mixed Voltage Environment ......................................... 98 7.3 3.3 Volt Translation ................... 98 7.3.2 SIO Bus Interfacing .......................... 98 8. Mechanical Dimensions .............................. 101 8.1 100-Lead PQFP (KH) Package - FS401LF .......................................................... 101 8.2 128-Lead PQFP Package, FS403 LF. 102 9. Revision History .......................................... 103 10. Ordering Information ............................... 104 10.1 Package Markings: ............................. 104 Tables Table 1. Pin Designations (FS401, 100-pin package) ...

Page 5

Architectural Overview Overall design principles are included in this section. Details of how to use and setup the FS400 are included in the Functional Description section, starting on page 75. RGB video inputs are asynchronously converted to either NTSC/PAL, ...

Page 6

FS401, FS403 1.2 Frame Store Memory Controller Inserted between the capture and the encoder engines the frame store has two functions act as a reservoir of pixels to match the incoming frame rate to the outgoing field or ...

Page 7

FS401, FS403 1.5 Typical System Configurations 1.5.1 External Scan Converter The FS403 has been optimized for scan converter designs. It provides a maximum amount of flexibility while minimizing system cost. When combined with a Zilog Z902xx Family or Philips P8xC055/145/845 ...

Page 8

FS401, FS403 1.5.2 Embedded Television Interface The FS401 has been optimized for television designs. With its built in microprocessor, the FS401 can run freely with minimal control from the television processor while providing complete plug-n-play capability. Simple commands can be ...

Page 9

FS401, FS403 1.5.4 Professional and Pro-Consumer Video Designs In the Professional and Pro-Consumer Video Market, Video quality, video timing accuracy, and Genlock are very important features. Also the system will use external ADCs and PLLs of the highest quality. Genlock ...

Page 10

FS401, FS403 80 81 100 1 2. Pin Assignments 2.1 100-Lead PQFP Package (FS401) Table 1. Pin Designations (FS401, 100-pin package) Pin Name Pin Name 1. V 31. TV_VSYNC DDPF 2. OSC1 32. TV_HSYNC 3. OSC1BUF 33 OSC2 ...

Page 11

FS401, FS403 2.2 128-Lead PQFP Package (FS403) Table 2. Pin Designations (FS403, 128-pin package) Pin Name Pin Name 1. OSC1 33 OSC1BUF 34. Reserved (V 3. OSC2 35. FLP_RST 4. OSC2BUF 36. Reserved ( 37. RESET ...

Page 12

FS401, FS403 3. Pin Descriptions Pin Name Pin Number Type/Value FS401/FS403 Clocks OSC1 2/1 TTL input OSC1BUF 3/2 LVTTL output OSC2 4/3 TTL input OSC2BUF 5/4 LVTTL output HS_IN 50/63 TTL input VS_IN 49/62 TTL input Global Controls INTCPUEN 59/77 ...

Page 13

FS401, FS403 Pin Name Pin Number Type/Value FS401/FS403 VGACLKDIV x/65 LVTTL 403 only output CLAMP_REF 46/55 LVTTL output EXADSEL x/23 TTL input 403 only Digital RGB Inputs or OSD/GPO Pins R x/59-56, x/41 TTL input 7-3 403 only R /OSDEN ...

Page 14

FS401, FS403 Pin Name Pin Number Type/Value FS401/FS403 OSDCLK x/19 LVTTL 403 only output Video Outputs Y/R/V 12/11 analog video CVBS/G/Y 15/14 analog video C/B/U 17/16 analog video CSYNC 20/20 LVTTL output TV_HSYNC 32/39 LVTTL output TV_VSYNC 31/38 LVTTL output ...

Page 15

FS401, FS403 Pin Name Pin Number Type/Value FS401/FS403 Frame Buffer Port D 15-0 79-76,73-62/ TTL input/ 100-97,94- LVTTL 91,88-81 output A 11-0 94-83/ LVTTL 118-107 output RAS\ 60/78 LVTTL output CAS\ 61/79 LVTTL output WE\ 58/76 LVTTL output DQM 57/75 ...

Page 16

FS401, FS403 Pin Name Pin Number Type/Value FS401/FS403 V SSAD 0 V 34, 35, 40, 43/ 43, 44, 49 SSPA 48/ SSPF 97/124 21, 22, 28, 29, 51, ...

Page 17

FS401, FS403 4. Control Register Definitions 4.1 Control Register Functions Control register functions are summarized in Table 3. Each internal register 16-bits wide. To access a register two 8-bit data words must be transferred. In the case ...

Page 18

FS401, FS403 4.2 Internal Micro-Controller Programming 4.2.1 Input Calibration The internal micro-controller needs to know what portion of the input video signal contains active video. Determining this information is referred to as Input Calibration. The input calibration information is used ...

Page 19

FS401, FS403 CCR_MAX_HAT Maximum Horizontal Active CCR_DEF_SVV Default Start of Vertical Video CCR_MIN_SVV Minimum Start of Vertical Video CCR_MAX_SVV Maximum Start of Vertical Video CCR_DEF_VAT Default Vertical Active CCR_MIN_VAT Minimum Vertical Active CCR_MAX_VAT Maximum Vertical Active An external controller can ...

Page 20

FS401, FS403 4.2.1.3 Input Calibration Tables The internal micro-controller can store input calibration information for four video modes when in both manual and auto input calibration mode. Setting the ENICTBL bit in the SCR register enables this feature. During a ...

Page 21

FS401, FS403 The pixels double in size in the vertical direction. The internal micro-controller also attempts to double pixels in the horizontal direction. This is possible for most video modes; however, with very large input images and very small output ...

Page 22

FS401, FS403 In the HCRS register: LNTCH Luminance Notch Filter CBP Chroma Bandpass Filter PEDSTL US NTSC Black Pedestal In the HCRES register: RGBGAIN 1x or 1.43x RGB Input Gain FREEZE Freeze the Input Image In the SCR register SFLK ...

Page 23

FS401, FS403 IHA Input Horizontal Active IHS Input Horizontal Samples OHO Output Horizontal Offset OVO Output Vertical Offset VSC Vertical Scaling Coefficient CR Control Register CRE Control Register Extended HSC Horizontal Scaling Coefficient FLK Flicker Filter AVT Active Video Threshold ...

Page 24

FS401, FS403 It is also possible to disable two portions of the internal micro-controllers program code. These are the video mode detect and the auto input calibration program code. The video mode detect program code is disabled by setting the ...

Page 25

FS401, FS403 4.4 Control Register Definitions Table 3. Control Register Map Function Reg. Bit # Name Type Input Horizontal Offset 0 7-0 IHO R/W 7-0 1 2-0 IHO R/W 10-8 Input Vertical Offset 2 7-0 IVO R/W 7-0 3 3-0 ...

Page 26

FS401, FS403 Function Reg. Bit # Name Type Output Horizontal Offset 20 7-0 OHO R/W 7-0 21 1-0 OHO R/W 9-8 Output Vertical Offset 22 7-0 OVO R/W 7-0 23 1-0 OVO R/W 9-8 Horizontal Scaling Coefficient 24 7-0 HSC ...

Page 27

FS401, FS403 Function Reg. Bit # Name Type Horizontal Pan Position 70 7-0 HPP R/W 7-0 71 7-0 HPP R/W 15-8 Vertical Pan Position 72 7-0 VPP R/W 7-0 73 7-0 VPP R/W 15-8 TV Pixels 74 7-0 TVP R/W ...

Page 28

FS401, FS403 4.5 Control Registers Definitions In the following definitions, range is defined as: {min value : [max value]} 4.5.1 IHO - Input Horizontal Offset Input Horizontal Offset Low ( IHO IHO IHO 7 6 Input Horizontal ...

Page 29

FS401, FS403 4.5.2 IVO - Input Vertical Offset Input Vertical Offset Low ( IVO IVO IVO 7 6 Input Vertical Offset High ( Register Bit# Bit Name 3, 2 3-0, 7-0 ...

Page 30

FS401, FS403 4.5.3 IHAW - Horizontal Active Width Horizontal Active Width Low ( IHAW IHAW IHAW 7 6 Horizontal Active Width High ( Register Bit# Bit Name 5, 4 1-0, 7-0 ...

Page 31

FS401, FS403 4.5.4 ILS - Input Lines Stored Input Lines Stored Low ( ILS ILS ILS 7 6 Input Lines Stored High ( Register Bit# Bit Name 7, 6 1-0, 7-0 ...

Page 32

FS401, FS403 4.5.5 IHS - Input Horizontal Samples Input Horizontal Samples Low ( IHS IHS IHS 7 6 Input Horizontal Samples High ( Register Bit# Name 9, 8 2-0, 7-0 IHS ...

Page 33

FS401, FS403 4.5.6 IHC - Input Horizontal Count Input Horizontal Count Low ( IHC IHC IHC 7 6 Input Horizontal Count High ( Register Bit# Bit Name B, A 1-0, 7-0 ...

Page 34

FS401, FS403 4.5.7 IVC - Input Vertical Count Input Vertical Count Low ( IVC IVC IVC 7 6 Input Vertical Count High ( Register Bit# Bit Name D, C 3-0, 7-0 ...

Page 35

FS401, FS403 4.5.8 VSC – Vertical Scaling Coefficient Vertical Scaling Coefficient ( VSC VSC VSC 7 6 Vertical Scaling Coefficient ( Register Bit# Bit Name E 7-0 VSC 7 ...

Page 36

FS401, FS403 4.5 Command Register Command Register Low (10 PEDSTL CBP LNTCH Command Register High(11 OFMT Reg Bit# Bit Name 10 0 RESET 10 1 CLKOFF 10 2 ADCOFF 10 ...

Page 37

FS401, FS403 4.5.10 SR – Status Register Status Register Low (12 Status Register High (13 Register Bit# Bit Name 12 3-0 REVID 13 6-0 FAMILY JANUARY 24, 2007 ...

Page 38

FS401, FS403 4.5.11 CRE – Command Register Extended Command Register Extended Low (14 VGAINTDET Command Register Extended High (15 EVVCLR SVVCLR EHVCLR Register Bit# Bit Name 14 5 VGAINTDET 14 4 VGAREFPOL ...

Page 39

FS401, FS403 4.5.12 Start Horizontal Active VGA Start Horizontal Active VGA Low (16 SHV SHV SHV 7 6 Start Horizontal Active VGA High (17 Register Bit# Bit Name 17, 16 2-0, ...

Page 40

FS401, FS403 4.5.13 End Horizontal Active VGA End Horizontal Active VGA Low (18 EHV EHV EHV 7 6 End Horizontal Active VGA High (19 Register Bit# Bit Name 19, 18 2-0, ...

Page 41

FS401, FS403 4.5.14 Start Vertical Active VGA Start Vertical Active VGA Low (1A SVV SVV SVV 7 6 Start Vertical Active VGA High (1B Register Bit# Bit Name 1B, 1A 2-0, ...

Page 42

FS401, FS403 4.5.15 End Vertical Active VGA End Vertical Active VGA Low (1C EVV EVV EVV 7 6 End Vertical Active VGA High (1D Register Bit# Bit Name 1D, 1C 2-0, ...

Page 43

FS401, FS403 4.5.16 Active Video Threshold Active Video Threshold Low (1E AVT AVT AVT 7 6 Active Video Threshold High (1F Register Bit# Bit Name 1F, 1E 7-0 AVT 7-0 Range: ...

Page 44

FS401, FS403 4.5.17 OHO - Output Horizontal Offset Output Horizontal Offset Low (20 OHO OHO OHO 7 6 Output Horizontal Offset High (21 Register Bit# Bit Name 21, 20 10-0 OHO ...

Page 45

FS401, FS403 4.5.18 OVO – Output Vertical Offset Output Vertical Offset Low (22 OVO OVO OVO 7 6 Output Vertical Offset High (23 Register Bit# Bit Name 23, 22 9-0 OVO ...

Page 46

FS401, FS403 4.5.19 HSC – Horizontal Scaling Coefficient Horizontal Scaling Coefficient (24 HSC HSC HSC 7 6 Horizontal Scaling Coefficient (25 Register Bit# Bit Name 25, 24 8-0 HSC 8-0 Range: ...

Page 47

FS401, FS403 4.5.20 Contrast Coefficient Contrast Coefficient Low (26 CON Contrast Coefficient High (27 Register Bit# Bit Name 26 5-0 CON 5-0 Range: {0:[63]} Example: CON = 21 hex; ...

Page 48

FS401, FS403 4.5.21 Brightness Coefficient Brightness Coefficient Low (28 BRT BRT BRT 7 6 Brightness Coefficient High (29 Register Bit# Bit Name 29, 28 7-0 BRT 7-0 Range: {-128:[127]} Example: BRT ...

Page 49

FS401, FS403 4.5.22 Sharpness Coefficient Sharpness Coefficient Low (2A Sharpness Coefficient High (2B Register Bit# Bit Name 2B, 2A 4-0 SHP 4-0 Range: {0:[31]} Example: SHP = 10 ...

Page 50

FS401, FS403 4.5.23 Flicker Filter Coefficient Flicker Filter Coefficient Low (2C Flicker Filter Coefficient High (2D Register Bit# Bit Name 2D, 2C 4-0 FLK 4-0 Range: {0:[21]} Filter ...

Page 51

FS401, FS403 4.5.24 Color Saturation Coefficient Color Saturation Coefficient Low (2E CSC Color Saturation Coefficient High (2F Register Bit# Bit Name 2F, 2E 5-0 CSC 5-0 Range: {0:[63]} Example: ...

Page 52

FS401, FS403 4.5.25 General Purpose Outputs General Purpose Outputs Low (34 GPO GPO GPO 7 6 General Purpose Outputs High (35 Register Bit# Bit Name 34 7-0 GPO 7-0 35 7-0 ...

Page 53

FS401, FS403 4.5.26 SCR – Software Control Register Software Control Register Low (60 ENICTBL RSTCALC RSTICAL Software Control Register High (61 SFLK SFLK SFLK Reg Bit# Bit Name 60 0 RESET ...

Page 54

FS401, FS403 61 2 CNTRSML 61 3 MICALNEW 61 7-4 SFLK 3-0 Reset Value: 0x8402 JANUARY 24, 2007 should be set to 0 for most applications. 0: Small input images are scaled horizontally to fill the output device. 1: Small ...

Page 55

FS401, FS403 4.5.27 SSR – Software Status Register Software Status Register Low (62 HSYNCACT VSYNCACT Software Status Register High (63 CHKSUM CHKSUM CHKSUM 7 6 Reg Bit# Bit Name 62 0 READY 62 ...

Page 56

FS401, FS403 4.5.28 HCRS – Hardware Control Register Shadow Hardware Control Register Shadow Low (64 PEDSTL CBP LNTCH Hardware Control Register Shadow High (65 OFMT Reg Bit# Bit Name 64 1 CLKOFF ...

Page 57

FS401, FS403 4.5.29 HCRES – Hardware Control Register Extended Shadow Hardware Control Register Extended Shadow Low (66 VGAINTDET Hardware Control Register Extended Shadow High (67 Reg Bit# Bit Name ...

Page 58

FS401, FS403 4.5.30 HPO – Horizontal Position Offset Horizontal Position Offset Low (68 HPO HPO HPO 7 6 Horizontal Position Offset High (69 HPO HPO HPO 15 14 Description: This offsets the horizontal position ...

Page 59

FS401, FS403 4.5.31 VPO – Vertical Position Offset Vertical Position Offset Low (6A VPO VPO VPO 7 6 Vertical Position Offset High (6B VPO VPO VPO 15 14 Description: This offsets the vertical position ...

Page 60

FS401, FS403 4.5.32 HSS – Horizontal Scale Step Horizontal Scale Step Low (6C HSS HSS HSS 7 6 Horizontal Scale Step High (6D HSS HSS HSS 15 14 Description: This offsets the horizontal scale ...

Page 61

FS401, FS403 4.5.33 VSS – Vertical Scale Step Vertical Scale Step Low (6E VSS VSS VSS 7 6 Vertical Scale Step High (6F VSS VSS VSS 15 14 Description: This offsets the vertical scale ...

Page 62

FS401, FS403 4.5.34 HPP – Horizontal Pan Position Horizontal Pan Position Low (70 HPP HPP HPP 7 6 Horizontal Pan Position High (71 HPP HPP HPP 15 14 Description: This controls the horizontal pan ...

Page 63

FS401, FS403 4.5.35 VPP – Vertical Pan Position Vertical Pan Position Low (72 VPP VPP VPP 7 6 Vertical Pan Position High (73 VPP VPP VPP 15 14 Description: This controls the vertical pan ...

Page 64

FS401, FS403 4.5.36 TVP – TV Pixels TV Pixels Low (74 TVP TVP TVP Pixels High (75 TVP TVP TVP 15 14 Description: Tells the internal controller the total number of ...

Page 65

FS401, FS403 4.5.37 TVL – TV Lines TV Lines Low (76 TVL TVL TVL Lines High (77 TVL TVL TVL 15 14 Description: Tells the internal controller the total number of ...

Page 66

FS401, FS403 4.5.38 CCR – Configuration Command Register Configuration Command Register Low (78 ADDR ADDR ADDR 7 6 Configuration Command Register High (79 Reg Bit# Bit Name 78 7-0 ADDR 7-0 ...

Page 67

FS401, FS403 4.5.39 CDR – Configuration Data Register Configuration Data Register Low (7A CDR CDR CDR 6 Configuration Data Register High (7B CDR CDR CDR 14 Description: Contains the value of the configuration parameter ...

Page 68

FS401, FS403 4.5.40 HOHOS – Hardware Output Horizontal Offset Shadow Hardware Output Horizontal Offset Shadow Low (7C HOHOS HOHOS HOHOS 7 6 Hardware Output Horizontal Offset Shadow High (7D HOHOS HOHOS HOHOS 15 14 ...

Page 69

FS401, FS403 4.5.41 HOVOS – Hardware Output Vertical Offset Shadow Hardware Output Vertical Offset Shadow Low (7E HOVOS HOVOS HOVOS 7 6 Hardware Output Vertical Offset Shadow High (7F HOVOS HOVOS HOVOS 15 14 ...

Page 70

FS401, FS403 4.6 Configuration Values Name Addr CCR_VERSION 0x00 CCR_FREQUENCY 0x01 CCR_FLT_FREQ 0x02 CCR_AVT 0x03 CCR_AVT_RGBGAIN 0x04 CCR_MIN_HAT 0x05 CCR_MAX_HAT 0x06 CCR_DEF_HAT 0x07 CCR_MIN_SHV 0x08 CCR_MAX_SHV 0x09 CCR_DEF_SHV 0x0A JANUARY 24, 2007 Reset R/W Size Description Value ...

Page 71

FS401, FS403 CCR_MIN_VAT 0x0B CCR_MAX_VAT 0x0C CCR_DEF_VAT 0x0D CCR_MIN_SVV 0x0E CCR_MAX_SVV 0x0F CCR_DEF_SVV 0x10 CCR_COUNTER 0x11 CCR_PIXEL_SIZE 0x12 CCR_LINE_SIZE 0x13 CCR_MICAL_HAT 0x14 CCR_MICAL_VAT 0x15 JANUARY 24, 2007 values. Expressed as a percentage of the horizontal total * 65536. R/W 16 ...

Page 72

FS401, FS403 CCR_MICAL_SHV 0x16 CCR_MICAL_SVV 0x17 CCR_HSS_MIN 0x18 CCR_HSS_MAX 0x19 CCR_VSS_MIN 0x1A CCR_VSS_MAX 0x1B CCR_HPX_MIN 0x1C CCR_HPX_MAX 0x1D CCR_VPX_MIN 0x1E CCR_VPX_MAX 0x1F CCR_GPO 0x20 CCR_IHC 0x21 CCR_IVC 0x22 CCR_HAT 0x23 JANUARY 24, 2007 when the internal micro-controller is in manual ...

Page 73

FS401, FS403 CCR_SHV 0x24 CCR_VAT 0x25 CCR_SVV 0x26 CCR_ICAL_TABLE_0_IVC 0x27 CCR_ICAL_TABLE_0_IHC 0x28 CCR_ICAL_TABLE_0_HAT 0x29 CCR_ICAL_TABLE_0_SHV 0x2A CCR_ICAL_TABLE_0_VAT 0x2B CCR_ICAL_TABLE_0_SVV 0x2C CCR_ICAL_TABLE_1_IVC 0x2D CCR_ICAL_TABLE_1_IHC 0x2E CCR_ICAL_TABLE_1_HAT 0x2F CCR_ICAL_TABLE_1_SHV 0x30 CCR_ICAL_TABLE_1_VAT 0x31 CCR_ICAL_TABLE_1_SVV 0x32 CCR_ICAL_TABLE_2_IVC 0x33 CCR_ICAL_TABLE_2_IHC 0x34 CCR_ICAL_TABLE_2_HAT 0x35 CCR_ICAL_TABLE_2_SHV 0x36 ...

Page 74

FS401, FS403 CCR_ICAL_TABLE_3_HAT 0x3B CCR_ICAL_TABLE_3_SHV 0x3C CCR_ICAL_TABLE_3_VAT 0x3D CCR_ICAL_TABLE_3_SVV 0x3E JANUARY 24, 2007 represents. R The accumulated HAT value used for this video mode. R The accumulated SHV value used for this video mode. R/W 16 ...

Page 75

FS401, FS403 5. Functional Description ADC_SEL R_DIG G_DIG B_DIG Built In Pattern Gain 8 Bit RED ADC RGB/YUV 8 Bit GRN Matrix ADC 8 Bit BLU ADC Vertical Scaler VGA Clamp PLL DRAM VGA_HSYNC PLL VGA_VSYNC Xtal_N Serial Bus Xtal_P ...

Page 76

FS401, FS403 2. IHC (read only) 3. IVC (read only) Capture Control also coordinates hand off of data to the Frame Store Controller. Input Horizontal Samples, IHS is the 11-bit terminal count of the number of pixels per horizontal line ...

Page 77

FS401, FS403 VGAPIX ADCLK Figure 6. FAZE Sets ADCK Sampling Edge on Incoming Pixels A/D converter power can be disconnected by setting the CR register ADCOFF bit. 5.1.4 24-bit Digital RGB Port (FS403 only) Extra pins are included on the ...

Page 78

FS401, FS403 5.1.6 Digital RGB Multiplexer The EXADSEL pin in conjunction with BIPGEN in the CRE register controls a triple 24-bit multiplexer that selects the source of RGB data to be supplied to the digital gain block. 24-bit RGB data ...

Page 79

FS401, FS403 0.1 Normalized Vertical Frequency FLK = 0 FLK = 4 FLK = 8 FLK = 12 FLK = 16 FLK = 20 Figure 8: Two ...

Page 80

FS401, FS403 Horizontal 14 Degrees 27 Degrees 45 Degrees Figure 10: FLK = 16, SHP = 16; Response at Horizontal, 14, 27, 45 Degrees 5.2 Frame Store ...

Page 81

FS401, FS403 5.2.1 SDRAM Interface The SDRAM Interface is designed to use a wide variety of 1Mx16 SDRAM parts. The critical parameters to use in selecting an SDRAM are listed below: <To be supplied later> CLK CS\ RAS\ CAS\ WE\ ...

Page 82

FS401, FS403 Input Vertical Offset, IVO is a twelve bit value that sets the vertical displacement of the captured active video relative to the vertical sync as show in Figure 12. Figure 12. Input Offset and Size Definitions Input Horizontal ...

Page 83

FS401, FS403 5.2.6 Zoom When zoom is activated by setting the ZOOM bit the Command Register, pixels are 2X replicated in the vertical and the horizontal directions. Pixels are replicated vertically by the Capture Engine that duplicates ...

Page 84

FS401, FS403 • Multiplexing alternatives on OSC2 must be done with an external multiplexer (perhaps controlled by a GPO bit) 5.3.2 Horizontal Scaler The Frame Store Controller passes pixels extracted from the external frame store memory to the Horizontal Scaler. ...

Page 85

FS401, FS403 5.3.5 Digital-to-Analog Converters Three 10-bit D/A converters accept data from either the video encoder or the YUV-to-RGB transcoder. Each output is a current source connected to the analog V resistor to develop the output voltage. Typically the DC ...

Page 86

FS401, FS403 Data received or transmitted on the SIODATA line must be stable for the duration of the positive-going SIOCLK pulse. Data on SIODATA may change only when SIOCLK = L. An SIODATA transition while SIOCLK = H is interpreted ...

Page 87

FS401, FS403 Figure 18. 7-bit Slave Address with Read/Write\ Bit SDA SCL Figure 19. 10-bit address transfer, upper two bits SDA ACK0 A7 A6 SCL Figure 20. 10-bit address transfer, lower eight bits There are five steps ...

Page 88

FS401, FS403 5.4.1 Data Transfer via Serial Interface If a slave device, such as the FS400 does not acknowledge the master device during a write sequence, SIODATA remains HIGH so the master can generate a stop signal. If the master ...

Page 89

FS401, FS403 5.4.2.2 Write to two consecutive control registers • Start signal • Slave Address byte (R/W bit = LOW) • Pointer Address byte • Data byte to register • Data byte to register (pointer address + 1) • Stop ...

Page 90

FS401, FS403 6. Specifications 6.1 Absolute Maximum Ratings (beyond which the device may be damaged) 1 Parameter Power Supply Voltages V DD (Measured DDAD (Measured to V SSAD ) V DDPA and V DDPF (Measured ...

Page 91

FS401, FS403 6.2 Operating Conditions Parameter V DD Digital Power Supply Voltage V DDAD, V DDDA A/D and D/A Supply Voltage V DDPA, V DDPF PLLs Supply Voltage A GND Analog Ground (Measured to D GND ) V RT Reference ...

Page 92

FS401, FS403 6.3 Electrical Characteristics Parameter Power Supply Currents I DD 3.3 volt current I DDAD 3.3 volt Analog current I DDDA 3.3 volt Analog current I DDPA 3.3 volt Analog current I DDPF 3.3 volt Analog current I DDT ...

Page 93

FS401, FS403 6.4 Switching Characteristics Parameter Clocks f CKIN_N NTSC Reference Clock Frequency f CKIN_P PAL Reference Clock Frequency f XTOL Reference Clock Frequency Tolerance t PWH Reference Clock Pulse Width, HIGH t PWL Reference Clock Pulse Width, LOW Reset ...

Page 94

FS401, FS403 6.5 System Performance Characteristics Parameter A/D Converter Input E A/D Integral Linearity Error, LI Independent E A/D Differential Linearity Error LD E Offset Voltage, Top OT E Offset Voltage, Bottom OB D/A Converter Output RES D/A Converter Resolution ...

Page 95

FS401, FS403 7. Application Notes 7.1 Circuit Example - PC RGB video signals and the vertical and horizontal sync signals are intercepted by tapping connections to the VGA connector. Typically, control of the FS400 will be through the serial interface. ...

Page 96

FS401, FS403 7.2 FS400 Design and Layout Considerations Careful circuit design and layout are key factors that insure a successful implementation of the FS400 in a product. The following guidelines will help insure that your design yields the best possible ...

Page 97

FS401, FS403 7.2.6 Video Output Filters • To reduce step noise on the D/A converter outputs, and to lower EMI, consider placing the 75Ω termination resistors and the first capacitor of the output filter close to the video output pins ...

Page 98

FS401, FS403 7.3 Interfacing to the FS400 in a Mixed Voltage Environment As many devices designed today, the FS400 is powered by +3.3 Volts. However, 5 Volt devices are still very common today and will continue to be used for ...

Page 99

FS401, FS403 For most applications this voltage difference is not an issue as the output drive low specification (V the SIO bus and the FS400 are both 0.4 Volts. However, in heavily loaded SIO busses the output V not always ...

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FS401, FS403 For applications with more than one supply, combinations of the above two circuits can be used. However, the simplest approach to this problem is to limit the loading on the SIO bus when possible. When this is not ...

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... FS401, FS403 8. Mechanical Dimensions 8.1 100-Lead PQFP (KH) Package - FS401LF Package is RoHS Compliant. Symbol Millimeters Min. Max. A 3. 2.55 2.75 B 0.25 0.40 C 0.10 0.25 D 23.60 24.20 D 19.80 20. 17.30 18.20 E1 13.80 14.20 e 0.65 BSC L 0.60 1.00 N 100 α 0 8° ccc - JANUARY 24, 2007 Notes Notes: 1. All dimensions and tolerances conform to ANSI Y14.5M-1982. ...

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FS401, FS403 8.2 128-Lead PQFP Package, FS403 LF Package is RoHS Compliant. Symbol FS403LF Min. Max 3.40 A1 0.25 B 0.13 0.28 D 23.20 BSC D 19.80 20. 17.2 BSC E1 13.80 14.10 e 0.50 BSC ...

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PRODUCT SPECIFICATION 9. Revision History 3/3/99: First Release, V1.0 4/2/99: Second Release, V1. added DPMS support & adaptive input filtering selection; p. 13, added GPO description; p. 17, moved OHO & OVO to list of registers used by ...

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... Focus enhancements – Semiconductor Group 22867 NW Bennett St., Suite #200 Hillsboro, OR 97124 U.S.A. Phone: (503) 615-7700 JANUARY 24, 2007 Screening Package Commercial 100 Lead PQFP Commercial 128 Lead PQFP Website: 104 COPYRIGHT © 1999 FOCUS ENHANCEMENTS, INC. PRODUCT SPECIFICATION REV. NO. 1.7 Package Marking FS401LF FS403LF Fax: (503) 615-4232 www.FOCUSsemi.com ...

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