FS401LF ETC2 [List of Unclassifed Manufacturers], FS401LF Datasheet - Page 81

• Manufacturer Part Number: FS401LF
• Description: PC to TV Video Scan Converters
• Manufacturer: ETC2 [List of Unclassifed Manufacturers]

FS401, FS403
5.2.1 SDRAM Interface
The SDRAM Interface is designed to use a wide variety of 1Mx16 SDRAM parts. The critical parameters
to use in selecting an SDRAM are listed below:
5.2.2 Phase Locked Loop
All SDRAM access is synchronized to the selected 4f
4f
PAL, multiplied x9, x11, or x14 by the Frame Store Controller Phase Locked Loop to create the 80 or 100
MHz SDRAM clock.
5.2.3 Input Offset and Size Control
Besides synchronizing all SDRAM access activities, the frame store controller also coordinates several
offset and size functions. These values are programmed into internal registers that control the setup of
the Frame Store Controller.
Input Horizontal Offset, IHO is an eleven bit value that sets the horizontal displacement of the captured
active video relative to the horizontal sync as show in Figure 12.
JANUARY 24, 2007
SC
clock is divided by two, then depending upon the outgoing video standard selection, either NTSC or
<To be supplied later>
D[15:0]
A[11:0]
DQM\
RAS\
CAS\
CLK
WE\
CS\
Figure 11. Timing Parameter Definition, SDRAM Interface
tFSSU
tFSHO
81
SC
clock derived from the OSC1 clock input. The
tFSDO
COPYRIGHT © 1999 FOCUS ENHANCEMENTS, INC.
tFSCO
tFSAO
PRODUCT SPECIFICATION
REV. NO. 1.7