FS401LF ETC2 [List of Unclassifed Manufacturers], FS401LF Datasheet - Page 96

• Manufacturer Part Number: FS401LF
• Description: PC to TV Video Scan Converters
• Manufacturer: ETC2 [List of Unclassifed Manufacturers]

FS401, FS403
7.2 FS400 Design and Layout Considerations
Careful circuit design and layout are key factors that insure a successful implementation of the FS400 in
a product. The following guidelines will help insure that your design yields the best possible results.
7.2.1 Video Input to A-D Converters
• Consider using a higher capacitor value and a lower resistor value in the input filter. For example, use
• Place the input lowpass filter shunt capacitor as close as possible to the input pin on the FS400. This
• Make the video input traces to the A-D converters as short as possible. Do not route other signal
• Consider adding diodes to V
7.2.2 Input ADC Phase Lock Loop
• The analog supply for the ADC PLL should always be clean and noise free to insure minimum jitter in
• When using the internal PLL, the supply line V
• Do not run other traces (especially clocks) near an external PLL.
• Use a solid ground plane under the FS400.
7.2.3 Memory Clock Phase Lock Loop
• When using an external PLL for the memory clock, series terminate the clock line, and keep the traces
• Avoid using an even multiple of the 4f
7.2.4 External SDRAM Interface
• Keep the traces from the FS400 to the external SDRAM as short as possible. Series terminate the
• Keep other traces, especially analog traces, away from the traces associated with the SDRAM. In
7.2.5 HSYNC and VSYNC
• The HSYNC and VSYNC inputs to the FS400 should be low pass filtered. 150Ω and 100pF work well.
• Consider adding diodes to V
JANUARY 24, 2007
100Ω and 100pF instead of 220Ω and 47pF. This will reduce noise at the ADC input.
capacitor acts as a reservoir of charge for the ADC’s input sampling circuitry, and limits the voltage
kickback from the sampling process.
traces (especially clocks!) parallel to these traces, or close to the ADC inputs of the FS400. External
interference coupled into the video can easily be discerned by the eye at very low levels.
FS400.
the PLL. This applies regardless of the PLL used, internal or external. Do not power other circuitry
from the PLL supply.
and a 4.7µF tantalum capacitor. If 50/60Hz ripple is an issue, consider using 47 or 100µF. Always
have a 1000pF to 0.1µF capacitor to remove high frequency noise.
as short as possible to reduce EMI.
multiples of the clocks that overlap are additive.
RAS\, CAS\, and FSCK_OUT as close as possible to the FS400. Consider series terminating the
address lines as well for further EMI reduction.
addition to 0.1µF bypass capacitors, consider adding 100 to 1000pF capacitors to reduce higher
frequency noise on the power supply.
Consider termination on these lines if the input cable length gives rise to significant reflections,
undershoot and overshoot.
DDAD
DD
and V
and V
SS
SC
SSAD
on these lines to reduce the risk of ESD damage to the FS400.
clock as your memory clock. This increases EMI since
on these lines to reduce the risk of ESD damage to the
DDPA
96
should be decoupled with a series resistor of 150Ω
COPYRIGHT © 1999 FOCUS ENHANCEMENTS, INC.
PRODUCT SPECIFICATION
REV. NO. 1.7