FS401LF ETC2 [List of Unclassifed Manufacturers], FS401LF Datasheet - Page 75

• Manufacturer Part Number: FS401LF
• Description: PC to TV Video Scan Converters
• Manufacturer: ETC2 [List of Unclassifed Manufacturers]

FS401, FS403
5. Functional Description
Details of how to connect and setup the FS400 are included in this section. Overall design principles are
in the Architectural Overview section. Operation of the FS400 is divided into four sections:
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•
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5.1 Capture Engine
A/D Converters, Built In Pattern Generator, RGB/YUV Matrix, Vertical Scaler and Flicker Filter comprise
the Capture Engine.
5.1.1 Timing and Control
Timing of the Capture Engine is derived from the Input Control Block which contains a series of counters
and decoders synchronized to the A/D sample clock, ADCK. ADCK is derived from a phase locked loop
referenced to the leading edge of horizontal sync.
Sync polarity is auto-detected by sensing the leading edge of horizontal sync HS_IN and vertical sync,
VS_IN. This edge is the reference for the phase-locked loop tracking the horizontal pixel count and the
vertical line counter.
Registers that interface with the Capture Timing and Control block are:
1. IHS
JANUARY 24, 2007
GRN
RED
G_DIG
BLU
R_DIG
B_DIG
ADC_SEL
VGA_HSYNC
VGA_VSYNC
Clamp
Capture Engine
Frame Store Controller
Encoder Engine
Serial Control Port
Embedded Microprocessor
Xtal_N
Xtal_P
Pattern
Built In
8 Bit
ADC
8 Bit
ADC
8 Bit
ADC
VGA
PLL
DRAM
PLL
Gain
RGB/YUV
Vertical
Scaler
Matrix
Serial Bus
Interface
(RGB
Figure 5. Functional Block Diagram
4. SHV (read only)
7-0
and A/D_SEL\ omitted on FS401)
FLP_RST
External
Memory
DRAM
Sync
75
Embedded
Processor
Horizontal
Scaler
OSD Overlay
Encoder
Video
COPYRIGHT © 1999 FOCUS ENHANCEMENTS, INC.
/3
YUV/RGB
Matrix
7. EVV (read only)
PRODUCT SPECIFICATION
DAC
DAC
DAC
9 Bit
9 Bit
9 Bit
REV. NO. 1.7
CHROMA_B_U
LUMA_R_V
CVBS_G_Y
HSYNC
CSYNC
VSYNC