cxd1944r Sony Electronics, cxd1944r Datasheet - Page 11

• Manufacturer Part Number: cxd1944r
• Description: Ieee1394 3-port 200mbps Cable Transceiver/arbiter
• Manufacturer: Sony Electronics

Physical-ID
R
CPS
RHB
IBR
GC
SPD
NP
ASTAT(n)
BSTAT(n)
Ch(n)
Con(n)
P(n) Fast
LoopInt
CPStatInt
CPStat
IDidIt
IllegalReq
ChipRev
Slow Pin
Slow Bit
ArbRstReq
Ping Timer
Name
Size
16
6
1
1
1
1
6
2
4
2
2
1
1
1
1
1
1
1
1
4
1
1
1
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
The address number of this node. Determined during Self-ID.
Indicates that this node is the root.
Cable power status.
Root Holding Bit. Attempts to become the root during next bus reset if set to “1”.
Initiate Bus Reset. Generates bus reset when possible after being set to “1”.
Cleared after bus reset.
Gap Count. Used to optimize gap time according to bus scale.
Indicates this node’s highest speed; 200Mbps when “01”, 100Mbps when “00”.
Indicates the number of ports on this node.
Indicates port n TPA status.
11 = Z, 01 = 1, 10 = 0, 00 = invalid
Indicates port n TPB status.
11 = Z, 01 = 1, 10 = 0, 00 = invalid
When the value is “1”, indicates that port n is the Child. “0” indicates Parent.
When the value is “1”, indicates that the active cable is connected to port n.
When the value is “1”, indicates that port n supports 200Mbps.
This is set to “1” when Tree-ID is not completed in time, which means that the
bus may be forming a loop.
Indicates a drop in cable power line voltage.
Same as CPS.
Indicates that this node generates the last bus reset. More than one node
may set this value.
Indicates an illegal LReq is detected.
Indicates the chip revision number.
Indicates XSLOW pin is set to LOW.
When set to “1”, the node acts as a 100Mbps PHY. Default is “0”.
Initiate the arbitrated bus reset. Cleared after bus reset.
50MHz Ping Timer count. A count starts when a configuration packet is trans-
mitted and stops when the first packet is received. The value may not be cleared
until the next configuration packet is sent.
–11–
Description
CXD1944R