cxd1944r Sony Electronics, cxd1944r Datasheet - Page 20

• Manufacturer Part Number: cxd1944r
• Description: Ieee1394 3-port 200mbps Cable Transceiver/arbiter
• Manufacturer: Sony Electronics

Additional Features
Short Bus Reset:
posed in the 1394 Trade Association by Apple Computer.
The standardization, however, has not been done yet.
The CXD1944R supports a short bus reset mode whose
reset pulse width is 1.4µs instead of the normal bus reset
pulse width of 166µs. This mode can be selected by con-
necting the TIO pin to V
a reset pulse, it will first arbitrate the bus according to the
fair protocol as a FairReq. If it gets the bus grant, it will
send a short bus reset pulse instead of a packet. This is
called “arbitrated bus reset”, which ensures all nodes can
detect the short bus reset pulse. Since it follows Fair pro-
tocol, it won’t disturb the isochronous cycle. This arbitrat-
ed bus reset can only work after the bus is initialized.
Before the bus initialization, the node will send a short
bus reset pulse immediately. In both cases, if a short bus
reset fails, the node will send a normal long bus reset, so
that the short bus reset mode can be used with an older
PHY which does not support a short bus reset mode.
device will send a long reset pulse. To request a short
arbitrated bus reset, write 1 to the ArbRsrReq bit in the
reset mode.
Power Class Programming
certain settings. PC [2 : 0] is used for this setting.
PC [2 : 0]
The short bus reset or arbitrated bus reset were pro-
If the IBR bit of the internal PHY register is set to 1, the
Power use or power supply from the cable requires
The power classes are defined as follows:
000
001
010
011
100
101
110
111
The node does not consume cable power. Also, power does not repeat.
The node operates on its own power, and a minimum of 15W is supplied to the cable.
The node operates on its own power, and a minimum of 30W is supplied to the cable.
The node operates on its own power and a minimum of 45W is supplied to the cable.
The node may use cable power. Maximum required power is 1W.
The node may use cable power. Maximum required power is 1W. A further 2W are required to
operate LINK and upper layer.
The node may use cable power. Maximum required power is 1W. A further 5W are required to
operate LINK and upper layer.
The node may use cable power. Maximum required power is 1W. A further 9W are required to
operate LINK and upper layer.
DD
. When the node needs to send
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Definition
Slow Mode:
environments, however, 200Mbps may be difficult to
operate; thus we have added the Slow Mode operation.
By connecting XSLOW pin to ground, or writing a “1” to
the Slow Bit of the internal PHY register, the device will
act as a 100Mbps PHY. D[2:3] is still active in the slow
mode.
Ping and Ping Timer:
the node received an R=0 and T=0 configuration packet,
it will send a Self-ID packet immediately as an acknowl-
edge. Since a LINK is not involved in this Self-ID trans-
mission, and it is very quick, a sender can know the exact
packet delay between the node and the remote node.
LINK can read a Ping timer count after a Self-ID acknowl-
edge. The Ping timer will be cleared and starts a count
only when a configuration packet is sent from the node.
The counter runs at 50MHz clock cycle. This feature is
thought useful to optimize a gap count of the bus.
The CXD1944R supports 200Mbps. In some cable
Ping is used to measure a node-node packet delay. If
CXD1944R