cxd1944r Sony Electronics, cxd1944r Datasheet - Page 18

• Manufacturer Part Number: cxd1944r
• Description: Ieee1394 3-port 200mbps Cable Transceiver/arbiter
• Manufacturer: Sony Electronics

Transmit Timing
Transmit:
through the LREQ pin, the PHY arbitrates for access to
the serial bus. If the PHY wins the arbitration, it grants the
bus to the LINK by asserting transmit on the CTL pin for
one SCLK cycle, followed by idle for one cycle. After
sampling the transmit state from the PHY, the LINK takes
over control of the interface by asserting either hold or
transmit on the CTL pins. The LINK asserts hold to keep
ownership of the bus while preparing data. The PHY
asserts the data-on state on the serial bus during this
time. When it is ready to begin transmitting a packet, the
LINK asserts transmit on the CTL pins along with the first
bits of the packet. After sending the last bits of the pack-
et, the link asserts either idle or hold on the on the CTL
pins for one cycle, and then idle for one additional cycle
before tristating those pins.
needs to send another packet without releasing the bus.
The PHY responds to this hold state by waiting the
required minimum time and then asserting transmit as
before. This function would be used after sending an
acknowledge if the LINK intends to send a unified
response, or to send consecutive isochronous packets
NOTES:
zz = Hi-Z
D0 to Dn = Packet data
This figure is for 100Mbps. For 200Mbps, D [0:3] is used.
When the LINK requests access to the serial bus
The hold state here indicates to the PHY that the LINK
Single Packet
LINK
D [0:1]
Continued Packet
LINK
CTL [0:1]
PHY
CTL [0:1]
PHY
CTL [0:1]
PHY
D [0:1]
PHY
D [0:1]
LINK
CTL [0:1]
LINK
D [0:1]
Dn–1
zz
zz
zz
00
00
zz
10
zz
zz
zz
11
00
zz
10
Dn
zz
zz
zz
00
00
zz
01
00
01
00
zz
zz
zz
zz
00
00
00
00
zz
zz
00
01
zz
zz
D0
zz
zz
10
00
00
zz
zz
–18–
D1
10
11
zz
zz
00
zz
zz
during a single cycle. The only requirement when send-
ing multiple packets during a single bus ownership is that
all must be transmitted at the same speed, since the
speed of the packet transmission is set before the first
packet.
the last packet for the current bus ownership, it releases
the bus by asserting idle on the CTL pins for two SCLK
cycles. The PHY begins asserting idle on the CTL pins
one clock after sampling idle from the link. Note that
whenever the D and CTL lines change “ownership”
between the PHY and the LINK, there is an extra clock
period allowed so that both sides of the interface can
operate on registered versions of the interface signals,
rather than having to respond to a CTL state on the next
cycle.
state before sending the first packet if implementation
permits the LINK to be ready to transmit as soon as bus
ownership is granted. The timing for a single packet
transmit operation is shown below. In the diagram, D0
through Dn are the data symbols of the packet; zz repre-
sents high impedance state.
D2
10
As noted above, when the LINK has finished sending
Note that it is not required that the LINK enter the hold
00
zz
zz
zz
00
zz
zz
zz
01
00
Dn
10
zz
zz
00
00
zz
zz
zz
zz
01
00
00
00
zz
zz
zz
zz
10
D0
zz
zz
zz
00
00
zz
10
D1
CXD1944R