cx82100 Conexant Systems, Inc., cx82100 Datasheet - Page 207

• Manufacturer Part Number: cx82100
• Description: Home Network Processor Hnp
• Manufacturer: Conexant Systems, Inc.

13
101306C
Clock Generation Interface Description
Conexant Proprietary and Confidential Information
The Clock Generation (CLKGEN) block generates internal and external clocks using two
programmable, fractional multiply phase locked loop (PLL) blocks, FCLK_PLL and
BCLK_PLL (Figure 13-1).
(VCO) and post-PLL generation logic which divides the output of each PLL to create a
series of sub-multiple clocks.
Clock generation operation is controlled by the PLL Bypass (PLLBP) input pin and by
three registers: FCLK PLL Register (PLL_F), BCLK PLL Register (PLL_B), and Low
Power Mode Register (LPMR).
PLLBP input low selects PLL Normal Mode (see Section 13.1) and PLLBP input high
selects PLL Bypass Mode for factory clock test operation (see Section 13.7).
The signals on the FCLKIO/GPIO39 and BCLKIO/GPIO38 pins are also controlled by
the PLLBP pin and by the GPIO_Sel7 and GPIO_Sel6 control bits in the GPIO Optional
Register (GPIO_OPT, see Section 9.3.1), respectively. FCLKIO/GPIO39 pin control is
summarized in Table 13-1 and BCLKIO/GPIO38 pin control is summarized in Table
13-2.
When in PLL Bypass Mode, the FCLKIO and BCLKIO pins are configured as inputs,
and are divided and used in place of the PLL outputs. When in PLL Normal Mode, the
FCLKIO and BCLKIO pins can be configured as outputs, and provide a means to
indirectly observe the frequency of the internal clocks generated by the PLLs.
Table 13-1. FCLKIO/GPIO39 Pin Usage Control
Table 13-2. BCLKIO/GPIO38 Pin Usage Control
Included in each block is the actual PLL circuit with a voltage-controlled oscillator
Notes:
1. Default at power up reset.
2. See Figure 13-1.
Notes:
1. Default at power up reset.
2. See Figure 13-1.
PLLBP Input
PLLBP Input
Pin Voltage
Pin Voltage
CX82100 Home Network Processor Data Sheet
Level
Level
High
High
Low
Low
Low
Low
GPIO Option Register (GPIO_OPT)
GPIO Option Register (GPIO_OPT)
GPIO_Sel7 Bit in
GPIO_Sel6 Bit in
Don’t care
Don’t care
0
1
0
1
BCLKIO/GPIO38 Pin
FCLKIO/GPIO39 Pin
Signal on
Signal on
GPIO39 1
GPIO38 1
EPCLK 2
XFCLK 2
XBCLK 2
UCLK 2
Pin Signal
Pin Signal
Direction
Direction
I/O
I/O
O
O
I
I
13-1