hy5ps1g831cfp Hynix Semiconductor, hy5ps1g831cfp Datasheet - Page 17

• Manufacturer Part Number: hy5ps1g831cfp
• Description: 1gb Ddr2 Sdram
• Manufacturer: Hynix Semiconductor

Rev. 0.1 /Dec 2006
IDD Test Conditions
(IDD values are for full operating range of Voltage and Temperature, Notes 1-5)
IDD0
IDD1
IDD2P
IDD2Q
IDD2N
IDD3P
IDD3N
IDD4W
IDD4R
IDD5B
IDD6
IDD7
Symbol
FLOATING is defined as inputs at VREF = VDDQ/2
SWITCHING is defined as: inputs changing between HIGH and LOW every other clock cycle (once per two clocks)
for address and control signals, and inputs changing between HIGH and LOW every other data transfer (once per
clock) for DQ signals not including masks or strobes.
Operating one bank active-precharge current; t CK = t CK(IDD), t RC = t RC(IDD), t RAS = t RAS
min(IDD) ; CKE is HIGH, CS is HIGH between valid commands;Address bus inputs are SWITCH-
ING;Data bus inputs are SWITCHING
Operating one bank active-read-precharge current ; IOUT = 0mA;BL = 4, CL = CL(IDD), AL
= 0; t CK = t CK(IDD), t RC = t RC (IDD), t RAS = t RASmin(IDD), t RCD = t RCD(IDD) ; CKE is HIGH,
CS is HIGH between valid commands ; Address bus inputs are SWITCHING ; Data pattern is same
as IDD4W
Precharge power-down current ; All banks idle ; t CK = t CK(IDD) ; CKE is LOW ; Other control
and address bus inputs are STABLE; Data bus inputs are FLOATING
Precharge quiet standby current;All banks idle; t CK = t CK(IDD);CKE is HIGH, CS is HIGH;
Other control and address bus inputs are STABLE; Data bus inputs are FLOATING
Precharge standby current; All banks idle; t CK = t CK(IDD); CKE is HIGH, CS is HIGH; Other
control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
Active power-down current; All banks open; t CK = t CK(IDD);
CKE is LOW; Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
Active standby current; All banks open; t CK = t CK(IDD), t RAS = t RASmax(IDD), t RP
= t RP(IDD); CKE is HIGH, CS is HIGH between valid commands; Other control and address bus
inputs are SWITCHING; Data bus inputs are SWITCHING
Operating burst write current; All banks open, Continuous burst writes; BL = 4, CL = CL(IDD),
AL = 0; t CK = t CK(IDD), t RAS = t RASmax(IDD), t RP = t RP(IDD); CKE is HIGH, CS is HIGH between
valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
Operating burst read current; All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL
= CL(IDD), AL = 0; t CK = t CK(IDD), t RAS = t RASmax(IDD), t RP = t RP(IDD); CKE is HIGH, CS is
HIGH between valid commands; Address bus inputs are SWITCHING;; Data pattern is same as
IDD4W
Burst refresh current; t CK = t CK(IDD); Refresh command at every t RFC(IDD) interval; CKE is
HIGH, CS is HIGH between valid commands; Other control and address bus inputs are SWITCH-
ING; Data bus inputs are SWITCHING
Self refresh current; CK and CK at 0V; CKE £ 0.2V; Other control and address bus inputs are
FLOATING; Data bus inputs are FLOATING
Operating bank interleave read current; All bank interleaving reads, IOUT = 0mA; BL = 4, CL
= CL(IDD), AL = t RCD(IDD)-1* t CK(IDD); t CK = t CK(IDD), t RC = t RC(IDD), t RRD = t RRD(IDD),
t RCD = 1* t CK(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are
STABLE during DESELECTs; Data pattern is same as IDD4R; - Refer to the following page for
detailed timing conditions
Conditions
Fast PDN Exit MRS(12) = 0
Slow PDN Exit MRS(12) = 1
HY5PS1G1631C(L)FP
HY5PS1G431C(L)FP
HY5PS1G831C(L)FP
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
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