hy5ps1g821m Hynix Semiconductor, hy5ps1g821m Datasheet - Page 48

• Manufacturer Part Number: hy5ps1g821m
• Description: 1gb Ddr2 Sdram
• Manufacturer: Hynix Semiconductor

Rev. 0.2 / Oct. 2005
The procedure for existing Self Refresh requires a sequence of commands. First, the clock must be stable
prior to CKE going back HIGH. Once Self Refresh Exit command is registered, a delay equal or longer than
the tXSNR or tXSRD must be satisfied before a valid command can be issued to the device. CKE must
remain high for the entire Self Refresh exit period tXSRD for proper operation. Upon exit from Self Refresh,
the DDR2 SDRAM can be put back into Self Refresh mode after tXSRD expires.NOP or deselect commands
must be registered on each positive clock edge during the Self Refresh exit interval. ODT should also be
turned off during tXSRD.
The Use of Self Refresh mode introduce the possibility that an internally timed refresh event can be missed
when CKE is raised for exit from Self Refresh mode. Upon exit from Self Refresh, the DDR2 SDRAM requires
a minimum of one extra auto refresh command before it is put back into Self Refresh mode.
- Device must be in the “All banks idle” state prior to entering Self Refresh mode.
- ODT must be turned off tAOFD before entering Self Refresh mode, and can be turned on again
- tXSRD is applied for a Read or a Read with autoprecharge command
- tXSNR is applied for any command except a Read or a Read with autoprecharge command.
CMD
when tXSRD timing is satisfied.
ODT
CKE
CK
CK
T0
tCH tCL
tCK
T1
tIS
T2
T3
tAOFD
tRP*
T4
tIS tIH
tIS
Refresh
Self
T5
T6
tIS
Tm
NOP
1HY5PS12421(L)M
HY5PS12821(L)M
> = tXSNR
NOP
> = tXSRD
NOP
Valid
Tn
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