IC DUAL 4-IN AND GATE 14SOIC

74HC21D,653

Manufacturer Part Number74HC21D,653
DescriptionIC DUAL 4-IN AND GATE 14SOIC
ManufacturerNXP Semiconductors
Series74HC
74HC21D,653 datasheet
 

Specifications of 74HC21D,653

Number Of Circuits2Package / Case14-SOIC (3.9mm Width), 14-SOL
Logic TypeAND GateNumber Of Inputs4
Current - Output High, Low5.2mA, 5.2mAVoltage - Supply2 V ~ 6 V
Operating Temperature-40°C ~ 125°CMounting TypeSurface Mount
ProductANDLogic FamilyHC
High Level Output Current- 5.2 mALow Level Output Current5.2 mA
Propagation Delay Time10 nsSupply Voltage (max)6 V
Supply Voltage (min)2 VMaximum Operating Temperature+ 125 C
Mounting StyleSMD/SMTMinimum Operating Temperature- 40 C
Lead Free Status / RoHS StatusLead free / RoHS CompliantOther names74HC21D-T
74HC21D-T
933756870653
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74HC21
Dual 4-input AND gate
Rev. 05 — 7 May 2009
1. General description
The 74HC21 is a high-speed Si-gate CMOS device and is pin compatible with low-power
Schottky TTL (LSTTL).
The 74HC21 provide the 4-input AND function.
2. Features
I
Low-power dissipation
I
Complies with JEDEC standard no. 7A
I
ESD protection:
N
HBM JESD22-A114E exceeds 2000 V
N
MM JESD22-A115-A exceeds 200 V
I
Multiple package options
I
Specified from 40 C to +80 C and from 40 C to +125 C.
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range
74HC21N
40 C to +125 C
74HC21D
40 C to +125 C
74HC21DB
40 C to +125 C
74HC21PW
40 C to +125 C
Name
Description
DIP14
plastic dual in-line package; 14 leads (300 mil)
SO14
plastic small outline package; 14 leads;
body width 3.9 mm
SSOP14
plastic shrink small outline package; 14 leads;
body width 5.3 mm
TSSOP14
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
Product data sheet
Version
SOT27-1
SOT108-1
SOT337-1
SOT402-1

74HC21D,653 Summary of contents

  • Page 1

    Dual 4-input AND gate Rev. 05 — 7 May 2009 1. General description The 74HC21 is a high-speed Si-gate CMOS device and is pin compatible with low-power Schottky TTL (LSTTL). The 74HC21 provide the 4-input AND function. 2. Features ...

  • Page 2

    ... NXP Semiconductors 4. Functional diagram 001aab975 Fig 1. Functional diagram & & 001aab974 Fig 3. IEC Logic symbol 5. Pinning information 5.1 Pinning 74HC21 n. GND 7 001aab972 Fig 5. Pin configuration SOT27-1 and SOT108-1 74HC21_5 Product data sheet Fig Fig n. Fig 6. Rev. 05 — 7 May 2009 74HC21 ...

  • Page 3

    ... NXP Semiconductors 5.2 Pin description Table 2. Pin description Symbol 1A, 1B, 1C, 1D n.c. 1Y GND 2Y 2A, 2B, 2C Functional description [1] Table 3. Function table Input [ HIGH voltage level LOW voltage level don’t care. 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). ...

  • Page 4

    ... NXP Semiconductors 8. Recommended operating conditions Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V) Symbol Parameter V supply voltage CC V input voltage I V output voltage input transition rise and fall rate T ambient temperature amb 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). ...

  • Page 5

    ... NXP Semiconductors 10. Dynamic characteristics Table 7. Dynamic characteristics GND = 0 V; test circuit see Figure Symbol Parameter Conditions t propagation nA, nB nY; pd delay see Figure transition time nY output; see power V = GND dissipation capacitance [ the same as t and PHL PLH [ the same as t and THL ...

  • Page 6

    ... NXP Semiconductors 11. Waveforms Measurement points are given in V and V are typical voltage output levels that occur with the output load Fig 7. Waveforms showing the input (nA, nB, nC, nD) to output (nY) propagation delays and the output transition times Table 8. Measurement points Type Input V M 74HC21 ...

  • Page 7

    ... NXP Semiconductors Test data is given in Table Definitions test circuit termination resistance should be equal to output impedance load capacitance including jig and probe capacitance. L Fig 8. Test circuit for measuring switching times Table 9. Test data Type Input V I 74HC21 V CC 74HC21_5 Product data sheet ...

  • Page 8

    ... NXP Semiconductors 12. Package outline DIP14: plastic dual in-line package; 14 leads (300 mil pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions UNIT max. min. max. mm 4.2 0.51 3.2 inches 0.17 0.02 0.13 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. ...

  • Page 9

    ... NXP Semiconductors SO14: plastic small outline package; 14 leads; body width 3 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.25 1.45 mm 1.75 0.25 0.10 1.25 0.010 0.057 inches 0.01 0.069 0.004 0.049 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...

  • Page 10

    ... NXP Semiconductors SSOP14: plastic shrink small outline package; 14 leads; body width 5 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.21 1. 0.25 0.05 1.65 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION IEC SOT337-1 Fig 11. Package outline SOT337-1 (SSOP14) ...

  • Page 11

    ... NXP Semiconductors TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...

  • Page 12

    ... Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Added type number 74HC21PW (TSSOP14 package). 74HC21_3 ...

  • Page 13

    ... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...

  • Page 14

    ... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Functional description . . . . . . . . . . . . . . . . . . . 3 7 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 5 11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 8 13 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 12 14 Revision history ...