UPD30121 NEC [NEC], UPD30121 Datasheet - Page 17

• Manufacturer Part Number: UPD30121
• Description: VR4121TM 64-/32-BIT MICROPROCESSOR
• Manufacturer: NEC [NEC]

1.2 Pin Status in Specific Status
UUCAS#/MRAS3#
ULCAS#/MRAS2#
Notes 1. This differs depending on the setting of the SCLK bit in the SDRAMMODEREG register.
Remark 0: low level, 1: high level, Hi-Z: high impedance
ROMCS (2:3)#
ROMCS (0:1)#
DATA (16:31)/
ADD25/SCLK
GPIO (16:31)
MRAS (0:1)#
DATA (0:15)
ADD (0:24)
Pin Name
LCDRDY
LCDCS#
BUSCLK
UCAS#
LCAS#
WR#
RD#
2. Maintains the state of the previous Full-speed Mode.
3. When used as the chip select for the ROM or extended ROM, this is the same as ROMCS (0:1)# pins.
4. When DBUS32 signal = 1, this becomes the high impedance state.
5. When DBUS32 signal = 1: See Note 7 below.
6. When DBUS32 signal = 1: low level is output.
7. Reset by the RSTSW# signal: The pin outputs a low level. (Self refresh)
8. Bus hold from the Suspend Mode: The state of the previous Full-speed Mode is maintained.
When used as the RAS for the extended DRAM, this is the same as MRAS (0:1)# pins.
When DBUS32 signal = 0, the high level is output.
When DBUS32 signal = 0: high level is output.
When DBUS32 signal = 0: high level is output.
Reset by the Deadman’s switch: The pin outputs a high level.
Bus hold from Full-speed Mode or Standby Mode: Outputs clocks.
When SCLK bit has a value of "1": outputs clock.
When SCLK bit has a value of "0": low level is output.
the RTC Reset
After Reset by
Note 4
Note 4
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
0/
0
0
0
0
0
0
Deadman’s Switch
or RSTSW# Signal
After Reset by the
Note 1
Note 3
Note 5
Note 5
Note 7
Note 7
Data Sheet U14691EJ1V0DS00
Hi-Z
0/
0
0
1
1
1
1
1
0
In the Suspend
Note 2
Note 2
Note 2
Note 2
Note 3
Note 6
Note 6
Note 2
Mode
1
1
1
1
1
0
0
Mode or Shut Down
by the HAL Timer
In the Hibernate
Note 3
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
0/
0
0
0
0
0
1
0
0
0
PD30121
During a Bus
Note 2
Note 3
Note 8
Hold
Hi-Z/
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
1
1
(1/4)
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