UPD30121 NEC [NEC], UPD30121 Datasheet - Page 51

• Manufacturer Part Number: UPD30121
• Description: VR4121TM 64-/32-BIT MICROPROCESSOR
• Manufacturer: NEC [NEC]

BUSCLK high-level width
BUSCLK low-level width
Address setup time (to BUSCLK)
Address setup time (to command signal )
Command signal setup time (to BUSCLK)
Command signal low-level width
Address hold time (from command signal )
Command signal recovery time
IOCHRDY sampling time
Command signal
IOCHRDY hold time (from command signal )
Data output setup time (to command signal )
Data output hold time (from command signal )
MEMCS16#/IOCS16# sampling start time
MEMCS16#/IOCS16# hold time (from command
signal )
Data input setup time
Data input hold time
(12) System bus parameter (IOCHRDY) (1/3)
Notes 1. Applied to BUSCLK pin when BSEL bit of BCUCNTREG3 register is 0.
CLKSEL2
Note 3
Remarks 1. Do not set CLKSEL (2:0) signal
Signal
2. Applied to BUSCLK pin when BSEL bit of BCUCNTREG3 register is 1.
3. With the V
4. The value of N is set by using the WISAA (0:2) bits of the BCUSPEEDREG register.
1
1
1
1
0
0
0
0
the system bus interface.
The value of T is set by using the CLKSEL (0:2) signals (TxD/CLKSEL2, RTS#/CLKSEL1, and
DTR#/CLKSEL0 pins).
delay time from IOCHRDY
2. Do not set CLKSEL (2:0) signal
CLKSEL1
Parameter
Signal
= 111.
= 110, 101 with 131 MHz model.
Note 4
1
1
0
0
1
1
0
0
R
4121, the MEMW#, MEMR#, IOW#, and IOR# signals are called the command signals for
Notes 3, 4
Notes 3, 4
CLKSEL0
Signal
1
0
1
0
1
0
1
0
Note 3
Note 4
Notes 3, 4
Note 3
Note 3
Note 3
Note 3
Notes 3, 4
Data Sheet U14691EJ1V0DS00
T (ns)
RFU
35
33
30
33
30
33
38
Symbol
t
t
t
t
t
BCLKH1
BCLKH2
BCLKL1
BCLKL2
t
t
t
t
t
t
t
t
t
t
t
AVSV1
t
RHCH
CHDV
AVCK
AVCL
CLCK
CLCH
CHAV
CHCL
CHRL
DVCL
CHSV
t
t
CLR
DS
DH
Note If the WISAA (0:2) bits are set to 100 or
Note 1
Note 2
Note 1
Note 2
WISAA2 Bit
Condition
1
1
0
0
0
0
Note
Note
1
1
high when BSEL bit of BCUCNTREG3
register is 0, the AC characteristics of t
and t
CLCK
WISAA1 Bit
are not guaranteed.
0
0
T
0
0
1
1
Note
Note
1
1
2
2
T
(N + 1)
T
T
T
MIN.
N
45
10
45
10
15
15
25
25
0
0
0
0
0
5
N
N
N
WISAA0 Bit
29
29
44
29
0
1
0
1
0
1
Note
Note
0
1
2
T
T
MAX.
N
N (TClock)
N + 29
PD30121
44
8
7
6
5
4
3
AVCK
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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