UPD30121 NEC [NEC], UPD30121 Datasheet - Page 8

• Manufacturer Part Number: UPD30121
• Description: VR4121TM 64-/32-BIT MICROPROCESSOR
• Manufacturer: NEC [NEC]

1. PIN FUNCTIONS
1.1 Pin Functions
8
ADD25/SCLK
ADD (0:24)
DATA (0:15)
DATA (16:31)/
GPIO (16:31)
LCDCS#
RD#
WR#
LCDRDY
ROMCS (2:3)#
ROMCS (0:1)#
CKE
UUCAS#/
MRAS3#
Remark # indicates active low.
(1) System bus interface signals
Signal
I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
I
This function differs depending on how the SMODE (1:2) signal is set.
<When SMODE (1:2) signal = 00>
<When SMODE (1:2) signal
This is a 25-bit address bus. The V
DRAM, ROM, LCD, or system bus (ISA).
This is a 16-bit data bus. The V
DRAM, ROM, LCD, or system bus.
This function differs depending on how the DBUS32 signal is set.
<When DBUS32 signal = 1>
<When DBUS32 signal = 0>
This is the LCD chip select signal. This signal is active when the V
high-speed system bus access using the ADD/DATA bus.
This is active when the V
This is active when the V
This is the LCD ready signal. Set this signal as active when the LCD controller is ready to receive
access from the V
<When DBUS32 signal = 1>
<When DBUS32 signal = 0>
This is the ROM or SROM chip select signal.
This is the SDRAM or SROM clock enable signal. When using neither SDRAM nor SROM, connect to
GND or leave open.
This function differs depending on how the DBUS32 signal is set or types of memory to be accessed.
<When DBUS32 signal = 1>
<When DBUS32 signal = 0>
The function differs with the setting of the DBUS32 signal.
This is a 25-bit address bus.
This is the operating clock for SDRAM and SROM.
This is the high-order 16 bits of the 32-bit data bus.
This bus is used for transmitting and receiving data between the V
This is a general-purpose I/O port.
This becomes the chip select signal for the extended ROM, SROM, DRAM, or SDRAM.
This is the ROM or SROM chip select signal.
When accessing DRAM (EDO type): This signal is active (UUCAS#) when a valid column address is
output via the ADD bus during access of DATA (24:31) in the 32-bit data bus.
When accessing SDRAM: This is the I/O buffer control signal (UUDQM#) that is used during access
of DATA (24:31) signal in the 32 bit data bus.
During 32-bit access of LCD/high-speed system memory: Byte enable signal that is used during
access of DATA (24:31) signal.
When accessing DRAM (EDO type): This is the DRAM's RAS signal (MRAS3#). This signal is
active when a valid row address is output via the ADD bus for the DRAM connected to the high-order
address.
When accessing SDRAM: This is the SDRAM's chip select signal (CS3#). This signal is active when
a command is issued for the SDRAM connected to the high-order address.
R
4121.
R
R
Data Sheet U14691EJ1V0DS00
4121 is reading data from the LCD, SDRAM, SROM, DRAM, or ROM.
4121 is writing data to the LCD, SDRAM, or DRAM.
00>
R
4121 uses this to transmit and receive data with a SDRAM, SROM,
R
4121 uses this to specify addresses for the SDRAM, SROM,
Function
R
4121 is performing LCD access and
R
4121 and the DRAM and ROM.
PD30121
(1/3)