UPD30121 NEC [NEC], UPD30121 Datasheet - Page 69

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UPD30121

Manufacturer Part Number
UPD30121
Description
VR4121TM 64-/32-BIT MICROPROCESSOR
Manufacturer
NEC [NEC]
Datasheet

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SCLK clock cycle
SCLK high-level width
SCLK low-level width
Data output delay time (from SCLK
Address output delay time (from SCLK
WR# output delay time (from SCLK
Data input setup time
Data input hold time
(22) SDRAM interface parameter
Note DATA (0:15) pins and DATA (16:31)/GPIO (16:31) pins in 32-bit mode
Notes 1. MRAS (0:1)#, ROMCS (2:3)#, UUCAS#/MRAS3#, ULCAS#/MRAS2#, UCAS#, LCAS#, CKE, and
Remark The broken lines indicate high impedance.
2. DATA (0:15) pins, and DATA (16:31)/GPIO (16:31) pins in 32-bit mode
ADD (9:24), SCAS#,
DATA (0:15) pins, and DATA (16:31)/GPIO (16:31) pins in 32-bit mode
DATA
SRAS# (output)
SCLK (output)
WR# (output)
Parameter
Note 2
Note 1
(input)
)
)
)
t
t
DSM
DSW
Data Sheet U14691EJ1V0DS00
t
SCLKH
Symbol
t
t
t
SCLKH
SCLKL
t
t
t
t
t
SCLK
DSM
DSW
SDH
DSA
SDS
t
DSA
Note
Note
t
Condition
SCLKL
t
SDS
t
SDH
MIN.
13.7
3.5
3.5
1.1
1.1
6.2
2.9
5.8
t
SCLK
MAX.
10.7
17.6
24.5
PD30121
Unit
ns
ns
ns
ns
ns
ns
ns
ns
69

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