CY2302 CYPRESS [Cypress Semiconductor], CY2302 Datasheet - Page 3

• Manufacturer Part Number: CY2302
• Description: Frequency Multiplier and Zero Delay Buffer
• Manufacturer: CYPRESS [Cypress Semiconductor]

How to Implement Zero Delay
Typically, Zero Delay Buffers (ZDBs) are used because a de-
signer wants to provide multiple copies of a clock signal in
phase with each other. The whole concept behind ZDBs is that
the signals at the destination chips are all going HIGH at the
same time as the input to the ZDB. In order to achieve this,
layout must compensate for trace length between the ZDB and
the target devices. The method of compensation is described
below.
External feedback is the trait that allows for this compensation.
The PLL on the ZDB will cause the feedback signal to be in
phase with the reference signal. When laying out the board,
match the trace lengths between the output being used for
feedback and the FBIN input to the PLL.
If it is desirable to either add a little delay, or slightly precede
the input signal, this may also be implemented by either mak-
ing the trace to the FBIN pin a little shorter or a little longer than
the traces to the devices being clocked.
Inserting Other Devices in Feedback Path
Another nice feature available due to the external feedback is
the ability to synchronize signals to the signal coming from
some other device. This implementation can be applied to any
Document #: 38-07154 Rev. **
device (ASIC, multiple output clock buffer/driver, etc.) that is
put into the feedback path.
Referring to Figure 2, if the traces between the ASIC/Buffer
and the destination of the clock signal(s) (A) are equal in length
to the trace between the buffer and the FBIN pin, the signals
at the destination(s) device will be driven HIGH at the same
time the Reference clock provided to the ZDB goes HIGH.
Synchronizing the other outputs of the ZDB to the outputs from
the ASIC/Buffer is more complex however, as any propagation
delay from the ZDB output to the ASIC/Buffer output must be
accounted for.
Figure 2. Six Output Buffer in the Feedback Path
Reference
Feedback
Signal
Input
Zero
Delay
Buffer
Buffer
ASIC/
CY2302
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