CY28442-2_05 CYPRESS [Cypress Semiconductor], CY28442-2_05 Datasheet
CY28442-2_05
Related parts for CY28442-2_05
CY28442-2_05 Summary of contents
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... VDD_SRC SRCT[1:5] CPUC[1:5] VDD_PCI PCI VDD_PCI PCIF VDD_48MHz 96_100_SSCT Divider 96_100_SSCC VDD_48MHz DOT96T Divider DOT96C VDD_48 USB • 3901 North First Street CY28442-2 Alviso Chipset SRC PCI REF DOT96 x5 Pin Configuration PCI2/SEL_CLKREQ VDD_REF VSS_REF 2 55 PCI_STP# ...
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... PWR 3.3V power supply for PLL. GND Ground for PLL precision resistor is attached to this pin, which is connected to the internal current reference. PWR 3.3V power supply for outputs. O, DIF Differential CPU clock outputs. GND Ground for outputs. I SMBus-compatible SCLOCK. I/O SMBus-compatible SDATA. CY28442-2 Description Page ...
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... Table 2. The block write and block read protocol is outlined in Table 3 while Table 4 outlines the corresponding byte write and byte read protocol. The slave receiver address is 11010010 (D2h). Description CY28442-2 Description ,V specifications. IL_FS IH_FS ...
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... Byte Read Protocol Bit Description 1 Start 8:2 Slave address – 7 bits 9 Write 10 Acknowledge from slave 18:11 Command Code – 8 bits 19 Acknowledge from slave 20 Repeated start 27:21 Slave address – 7 bits 28 Read 29 Acknowledge from slave 37:30 Data from slave – 8 bits 38 NOT Acknowledge 39 Stop CY28442-2 Page ...
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... PCI5 Output Enable 0 = Disabled Enabled PCI4 PCI4 Output Enable 0 = Disabled Enabled PCI3 PCI3 Output Enable 0 = Disabled Enabled PCI2 PCI2 Output Enable 0 = Disabled Enabled Reserved, Set = 1 Reserved, Set = 1 Reserved, Set = 1 PCIF1 PCIF1 Output Enable 0 = Disabled Enabled CY28442-2 Description Description Description Page ...
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... Driven when CPU_STP# asserted,1 = Tri-state when CPU_STP# asserted SRC[T/C] PWRDWN Drive Mode 0 = Driven when PD asserted,1 = Tri-state when PD asserted CPU[T/C]2 PWRDWN Drive Mode 0 = Driven when PD asserted,1 = Tri-state when PD asserted CPU[T/C]1 PWRDWN Drive Mode 0 = Driven when PD asserted,1 = Tri-state when PD asserted CY28442-2 Description Description Description Page ...
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... SRC[T/C]3 stoppable by CLKREQ#B pin 0 = SRC[T/C]3 not controlled by CLKREQ#B pin SRC[T/C]1 CLKREQ#B control 1 = SRC[T/C]1 stoppable by CLKREQ#B pin 0 = SRC[T/C]1 not controlled by CLKREQ#B pin RESERVED SRC[T/C]4 CLKREQ#A control 1 = SRC[T/C]4 stoppable by CLKREQ#A pin 0 = SRC[T/C]4 not controlled by CLKREQ#A pin CY28442-2 Description Description Description Description Page ...
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... SRC[T/C]5 CLKREQ#A control 1 = SRC[T/C]5 stoppable by CLKREQ#A pin 0 = SRC[T/C]5 not controlled by CLKREQ#A pin SRC[T/C]3 CLKREQ#A control 1 = SRC[T/C]3 stoppable by CLKREQ#A pin 0 = SRC[T/C]3 not controlled by CLKREQ#A pin SRC[T/C]1 CLKREQ#A control 1 = SRC[T/C]1 stoppable by CLKREQ#A pin 0 = SRC[T/C]1 not controlled by CLKREQ#A pin CY28442-2 Description Description Description Page ...
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... AT Parallel The CY28442-2 requires a Parallel Resonance Crystal. Substituting a series resonance crystal will cause the CY28442-2 to operate at the wrong frequency and violate the ppm specification. For most applications there is a 300-ppm frequency shift between series and parallel crystals due to incorrect loading. Crystal Loading Crystal loading plays a critical role in achieving low ppm perfor- mance ...
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... This diagram and description is applicable to valid CPU frequencies 100, 133, 166, 200, 266, 333, and 400 MHz. In the event that PD mode is desired as the initial power-on state, PD must be asserted HIGH in less than 10 µs after asserting Vtt_PwrGd#. Figure 4. Power-down Assertion Timing Waveform CY28442-2 Page ...
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... CPUT = HIGH and CPUC = LOW. There is no change to the output drive current values during the stopped state. The CPUT is driven HIGH with a current value equal (Iref), and the CPUC signal will be tri-stated. Tstable <1.8nS Tdrive_PWRDN# <300µS, >200mV Figure 6. CPU_STP# Assertion Waveform CY28442-2 Page ...
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... CPUC(Stoppable) DOT96T DOT96C Figure 8. CPU_STP#= Driven, CPU_PD = Driven, DOT_PD = Driven CPU_STOP# PD CPUT(Free Running) CPUC(Free Running) CPUT(Stoppable) CPUC(Stoppable) DOT96T DOT96C Figure 9. CPU_STP# = Tri-state, CPU_PD = Tri-state, DOT_PD = Tri-state Document #: 38-07691 Rev. *B Tdrive_CPU_STP#,10nS>200mV Figure 7. CPU_STP# Deassertion Waveform CY28442-2 1.8mS 1.8mS Page ...
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... SU Tsu Figure 10. PCI_STP# Assertion Waveform Tdrive_SRC Tsu Figure 11. PCI_STP# Deassertion Waveform 0.2-0.3mS W ait for Sample Sels Delay VTT_PW RGD# State 1 State 2 On Figure 12. VTT_PWRGD# Timing Diagram CY28442-2 Device is not affected, VTT_PW RGD# is ignored State 3 On Page ...
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... VDD_A = 2.0V S0 Power Off Figure 13. Clock Generator Power-up/Run State Diagram Document #: 38-07691 Rev VTT_PWRGD# = Low Delay >0.25mS S3 VDD_A = off Normal Operation VTT_PWRGD# = toggle CY28442-2 S2 Sample Inputs straps Wait for <1.8ms Enable Outputs Page ...
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... SDATA, SCLK Except internal pull-up resistors, 0 < V Except internal pull-down resistors, 0 < – max. load and freq. per Figure 15 PD asserted, Outputs Driven PD asserted, Outputs Tri-state Current in tri-state mode CY28442-2 Min. Max. Unit –0.5 4.6 V –0.5 4.6 V –0 0.5 VDC DD – ...
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... Measured at crossing point V OX Measured at crossing point V OX Measured at crossing point V OX Measured from V = 0.175 0.525V OH Determined as a fraction of 2*(T – T )/( Math averages Figure 15 Math averages Figure 15 CY28442-2 Min. Max. Unit 47.5 52.5 % 69.841 71.0 ns – 10 – 500 ps – 300 ppm 9.997001 10 ...
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... Math averages Figure 15 Math averages Figure 15 See Figure 15. Measure SE Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measurement at 2.4V Measurement at 0.4V Measured between 0.8V and 2.0V Measurement at 1.5V Measurement at 1.5V Measured at crossing point V Measured at crossing point V Measured at crossing point V Measured at crossing point V CY28442-2 Min. – V –0.3 – 9.997001 10.00300 OX 9.997001 10.05327 OX 9.872001 10 ...
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... Math averages Figure 15 See Figure 15. Measure SE Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measurement at 2.4V Measurement at 0.4V Measured between 0.8V and 2.0V Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measured between 0.8V and 2.0V Measurement at 1.5V Output under Test tDC 3. CY28442-2 Min. = 0.175 to 175 – – – 660 –150 250 – V –0.3 – 45 20.83125 20.83542 20 ...
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... Package Type CY28442 Product Flow Commercial, 0° to 85°C Commercial, 0° to 85°C ...
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... SEATING 0.279[0.011] PLANE 2 C system, provided that the system conforms to the I CY28442-2 DIMENSIONS IN MM[INCHES] MIN. MAX. REFERENCE JEDEC MO-153 PACKAGE WEIGHT 0.42gms PART # Z5624 STANDARD PKG. ZZ5624 LEAD FREE PKG. 0.508[0.020] 0.762[0.030] 0° ...
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... Document History Page Document Title: CY28442-2 Clock Generator for Intel Document Number: 38-07691 REV. ECN NO. Issue Date ** 237627 See ECN *A 378059 See ECN *B 390510 See ECN Document #: 38-07691 Rev. *B Alviso Chipset Orig. of Change RGL New Data Sheet RGL Minor Change: Corrected typo in the label of the diagram from PLL4 to PLL3 ...