CY2DP818-2_08 CYPRESS [Cypress Semiconductor], CY2DP818-2_08 Datasheet
CY2DP818-2_08
Related parts for CY2DP818-2_08
CY2DP818-2_08 Summary of contents
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... Designed for data communications clock management appli- cations, the large fanout from a single input reduces loading on the input clock. The CY2DP818-2 is ideal for both level translations from single-ended to LVPECL and for the distribution of LVPECL based clock signals. The Cypress CY2DP818-2 has configurable input functions. ...
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... See InConfig, below. single pin LVPECL Differential outputs. LVTTL/LVCMOS Converts inputs from the default LVPECL/LVDS (logic = 0) to LVTTL/LVCMOS (logic = 1) See Input Receiver Configuration for Differential or LVTTL/LVCMOS additional information CY2DP818-2 Description table, Figure 6 and Figure 7 for Page [+] Feedback [+] Feedback [+] Feedback ...
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... Single ended, non inverting, inverting, void of bias resistors Low voltage differential signaling Low voltage pseudo (positive) emitter coupled logic LVTTL/LVCMOS Input Logic Input Logic Output Logic Q Pins, Q1A or Q1 Input Input Input Input CY2DP818-2 Min Typ Max Unit 1.5 2.0 mA/ MHz 350 mA 50 ...
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... A Conditions Guaranteed Logic High Level Guaranteed Logic Low Level V = Max Max Max (Max Min – CY2DP818-2 Min Max –0.3 4.6 –0 0.3 DD applied –0 0 –0 0.9 DD ÷ 2 – – ...
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... Min User-defined by VTT RTT Max GND DD OUT Description Conditions 45% to 55% duty cycle Standard load circuit Figure 2. Driver Design CY2DP818-2 Min Typ Max ohm 1000 – 3600 ohm – – 300 ohm 300 1200 I = –12 mA 2.1 – ...
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... Differential T PLH T PHL 0V Differential QXA - QXB 150 B GND 150 Standard Termination V 2.0V I(A) V I(B) 1.6V ≤ 1 ns; pulse rerate = 50 Mpps; pulse width = 10 ± 0.2 ns. and CY2DP818-2 [2,3,4,5] TPA 50 TPC VDD-2V 50 TPB 1.4 V 1.0 V 1.4 V 1.0 V 80% 20% [2,3,4,5] TPA 50 TPC 50 TPB VOC VOD Next Device – Page ...
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... INPUT A LVCM OS / LVTTL INPUT B GND InConfig LVTTL/LVCMOS 1 Ordering Information Part Number CY2DP818ZI-2 CY2DP818ZI-2T CY2DP818ZC-2 CY2DP818ZC-2T Pb Free Devices CY2DP818ZXI-2 CY2DP818ZXI-2T CY2DP818ZXC-2 CY2DP818ZXC-2T Note 6. LVPECL or LVDS differential input value. Document #: 38-07588 Rev. *A PRELIMINARY 150 10pF GND 150 Standard Termination 1.4V 1.0V 0.0V tF Figure 7. LVDS/LVPECL & ...
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... Package Drawing and Dimensions Document #: 38-07588 Rev. *A PRELIMINARY Figure 8. 38-Pin TSSOP (4.40 mm Body) Z38 CY2DP818-2 51-85151-*A Page [+] Feedback [+] Feedback [+] Feedback ...
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... Document History Page Document Title: CY2DP818-2 1:8 Clock Fanout Buffer Document Number: 38-07588 Submission Rev. ECN No. Date ** 129879 11/07/03 *A 2595534 10/23/08 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress ...