p520-10dc PhaseLink Corp., p520-10dc Datasheet
p520-10dc
Manufacturer Part Number
p520-10dc
Description
Low Phase Noise Vcxo With Multipliers
Manufacturer
PhaseLink Corp.
Datasheet
1.P520-10DC.pdf
(8 pages)
FEATURES
•
•
•
•
•
•
•
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DESCRIPTION
PLL520-10 is a VCXO IC specifically designed to
pull frequency fundamental crystals from 65MHz to
130MHz, with an integrated Phase Locked Loop for
selectable 1x (no PLL), 2x, 4x or 8x multipliers. Its
design was optimized to tolerate higher limits of
interelectrode capacitance and bonding capacitance
to improve yield. It achieves very low current into the
crystal resulting in better overall stability. Its internal
varicaps allow an on chip frequency pulling,
controlled by the VCON input.
BLOCK DIAGRAM
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/14/06 Page 1
VCON
SEL
X+
X-
65MHz to 130MHz Fundamental Mode Crystal.
Output range: 65MHz – 800MHz (selectable 1x,
2x, 4x and 8x multipliers).
Low Injection Power for crystal 50uW.
Available outputs: PECL, LVDS, or CMOS (High
Drive (30mA) or Standard Drive (10mA) output).
Integrated variable capacitors.
Supports 3.3V-Power Supply.
Available in die form.
Thickness 10 mil.
Low Phase Noise VCXO with multipliers (for 65-130MHz Fund Xtal)
integrated
Oscillator
Amplifier
varicaps
w/
PLL by-pass
Locked
(Phase
Loop)
PLL
PLL520-10
OE
Q
Q
DIE CONFIGURATION
DIE SPECIFICATIONS
OUTPUT SELECTION AND ENABLE
Pad #9:
Pad #30: Logical states defined by PECL levels if OE_SELECT (pad
Y
SEL3^
SEL2^
VCON
XOUT
OE_SELECT
CTRL
1 (Default)
OUTSEL1
(Pad #18)
Pad dimensions
(Pad #9)
XIN
OE
X
Reverse side
(0,0)
Thickness
0
0
1
1
0
Name
Bond to GND to set to “0”, bond to VDD to set to “1”
#9) is “1”
Logical states defined by CMOS levels if OE_SELECT is “0”
Size
26
27
28
29
30
31
25
1
C502A
A1313-13A
24
1 (Default)
0 (Default)
2
OE_CTRL
(Pad #30)
Die ID:
OUTSEL0
(Pad #25)
23
3
0
1
0
1
0
1
22
4
21
80 micron x 80 micron
5
65 mil
Tri-state
Output enabled
Output enabled
Tri-state
PLL520-10
High Drive CMOS
Standard CMOS
LVDS
PECL (default)
20
62 x 65 mil
Selected Output
6
Value
10 mil
GND
19
State
7
18
8
10
12
11
17
16
15
14
13
(1550,1475)
9
GNDBUF
CMOS
LVDSB
PECLB
VDDBUF
VDDBUF
PECL
LVDS
OE_SEL^
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