PS12001ARN-0 POWERTIP [Powertip Technology], PS12001ARN-0 Datasheet - Page 44

• Manufacturer Part Number: PS12001ARN-0
• Description: OUTLINE DIMENSION & BLOCK DIAGRAM
• Manufacturer: POWERTIP [Powertip Technology]

ST7066U
# # # # " " " " Read Busy Flag and Address
# # # # " " " " Write Data to CGRAM or DDRAM
# # # # " " " " Read Data from CGRAM or DDRAM
V2.0
Write binary 8-bit data to DDRAM/CGRAM.
The selection of RAM from DDRAM, CGRAM, is set by the previous address set instruction
: DDRAM address set, CGRAM address set. RAM set instruction can also determine the AC
direction to RAM.
After write operation, the address is automatically increased/decreased by 1, according to
the entry mode.
Read binary 8-bit data from DDRAM/CGRAM.
The selection of RAM is set by the previous address set instruction. If address set instruction of RAM is not
performed before this instruction, the data that read first is invalid, because the direction of AC is not
determined. If you read RAM data several times without RAM address set instruction before read operation,
you can get correct RAM data from the second, but the first data would be incorrect, because there is no time
margin to transfer RAM data.
In case of DDRAM read operation, cursor shift instruction plays the same role as DDRAM address
set instruction : it also transfer RAM data to output data register. After read operation address counter is
automatically increased/decreased by 1 according to the entry mode. After CGRAM read operation, display
shift may not be executed correctly.
* In case of RAM write operation, after this AC is increased/decreased by 1 like read operation. In this time,
AC indicates the next address position, but you can read only the previous data by read instruction.
When BF = “High”, indicates that the internal operation is being processed.So during this time the next
instruction cannot be accepted.
The address Counter (AC) stores DDRAM/CGRAM addresses, transferred from IR.
After writing into (reading from) DDRAM/CGRAM, AC is automatically increased (decreased) by 1.
Code
Code
Code
RS
0
RS
RS
1
1
RW
1
RW
RW
0
1
DB7
BF
DB7
DB7
D7
D7
DB6
AC6 AC5 AC4 AC3 AC2
DB6
DB6
D6
D6
DB5
DB5
DB5
D5
D5
DB4
DB4
D4
D4
21/42
DB4
DB3
DB3
D3
D3
DB3
DB2
DB2
D2
D2
DB2
DB1
DB1
D1
D1
DB0
DB0
DB1
AC1 AC0
D0
D0
DB0
2001/03/01