RM5231-250-Q PMC [PMC-Sierra, Inc], RM5231-250-Q Datasheet - Page 16

• Manufacturer Part Number: RM5231-250-Q
• Manufacturer: PMC [PMC-Sierra, Inc]

Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use
Document ID: PMC-2002165, Issue 1
3.13 Virtual to Physical Address Mapping
Figure 4 CP0 Registers
The RM5231 provides three modes of virtual addressing:
•
•
•
This mechanism is available to system software to provide a secure environment for user
processes. Bits in the CP0 Status register determine which virtual addressing mode is used. In the
user mode, the RM5231 provides a single, uniform virtual address space of 1TB (2 GB in 32-bit
mode).
When operating in the kernel mode, four distinct virtual address spaces, totalling over 2.5 TB (4
GB in 32-bit mode), are simultaneously available and are differentiated by the high-order bits of
the virtual address.
The RM5231 processors also support a supervisor mode in which the virtual address space over 2
TB (2.5 GB in 32-bit mode), divided into three regions based on the high-order bits of the virtual
address.
When the RM5231 is configured as a 64-bit microprocessor, the virtual address space layout is an
upward compatible extension of the 32-bit virtual address space layout.
Figure 5 shows the address space layout for 32-bit operation.
LLAddr
user mode
kernel mode
supervisor mode
17*
47
0
PageMask
EntryHi
TagLo
10*
28*
5*
(entries protected
from TLBWR)
TLB
Used for memory
management
EntryLo0
EntryLo1
2*
3*
TagHi
29*
RM5231™ Microprocessor with 32-bit System Bus Data Sheet
* Register number
Random
Config
Wired
Index
PRId
15*
16*
0*
1*
6*
Context
Status
Count
ECC
EPC
12*
14*
26*
4*
9*
Used for exception
BadVAddr
CacheErr
ErrorEPC
Compare
XContext
Cause
processing
11*
13*
20*
27*
30*
8*
Released
16