RM5261A-300-HI PMC [PMC-Sierra, Inc], RM5261A-300-HI Datasheet - Page 20

• Manufacturer Part Number: RM5261A-300-HI
• Manufacturer: PMC [PMC-Sierra, Inc]

Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use
Document ID: PMC-2002240, Issue 2
Cache protocols supported for the data cache are:
1. Uncached
2. Write-back
3. Write-through with write allocate
4. Write-through without write allocate
The most commonly used write policy is write-back, where a store to a cache line does not
immediately cause main memory to be updated. This increases system performance by reducing
bus traffic and eliminating the bottleneck of waiting for each store operation to finish before
issuing a subsequent memory operation. Software can, however, select write-through on a per-
page basis when appropriate, such as for frame buffers.
Associated with the data cache is the store buffer. When the RM5261A executes a store
instruction, this single-entry buffer gets written with the store data while the tag comparison is
performed. If the tag matches, then the data is written into the data cache in the next cycle that the
data cache is not accessed (the next non-load cycle). The store buffer allows the RM5261A to
execute a store every processor cycle and to perform back-to-back stores without penalty. In the
event of a store immediately followed by a load to the same address, a combined merge and cache
write occurs such that no penalty is incurred. The RM5261A cache attributes for both the
instruction and data caches are summarized in Table 3.
Data loads and instruction fetches from uncached memory space are brought in from the main
memory to the register file and the execution unit, respectfully. The caches are not accessed.
Data stores to uncached memory space go directly to the main memory without updating the
data cache.
Loads and instruction fetches first search the cache, reading main memory only if the desired
data is not cache resident. On data store operations, the cache is first searched to determine if
the target address is cache resident. If it is resident, the cache contents are updated, and the
cache line is marked for later write-back. If the cache lookup misses, the target cache line is
first brought into the cache and then the write is performed as above.
Loads and instruction fetches first search the cache, reading main memory only if the desired
data is not cache resident. On data store operations, the cache is first searched to determine if
the target address is cache resident. If it is resident, the cache contents are updated and main
memory is written, leaving the write-back bit of the cache line unchanged. If the cache lookup
misses, the target line is first brought into the cache and then the write is performed as above.
Loads and instruction fetches first search the cache, reading main memory only if the desired
data is not cache resident. On data store operations, the cache is first searched to determine if
the target address is cache resident. If it is resident, the cache contents are updated and main
memory is written, leaving the write-back bit of the cache line unchanged. If the cache lookup
misses, then only main memory is written.
RM5261A™ Microprocessor with 64-Bit System Bus Data Sheet
Preliminary
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