LTC3414 LINER [Linear Technology], LTC3414 Datasheet - Page 12

• Manufacturer Part Number: LTC3414
• Description: 4A, 4MHz, Monolithic Synchronous Step-Down Regulator
• Manufacturer: LINER [Linear Technology]

LTC3414
APPLICATIO S I FOR ATIO
12
Design Example
As a design example, consider using the LTC3414 in an
application with the following specifications:
Because efficiency is important at both high and low load
current, Burst Mode operation will be utilized.
First, calculate the timing resistor:
Use a standard value of 294k. Next, calculate the inductor
value for about 40% ripple current at maximum V
Using a 0.47 H inductor results in a maximum ripple
current of:
C
satisfy the output voltage ripple requirement and the bulk
capacitance needed for loop stability. For this design, a
22 F ceramic capacitor and a 470 F tantalum capacitor
will be used.
C
Decoupling the PV
tors and a 330 F tantalum capacitor is adequate for most
applications.
The burst clamp and output voltage can now be pro-
grammed by choosing the values of R1, R2, and R3. The
voltage on pin MODE will be set to 0.49V by the resistor
divider consisting of R2 and R3. A burst clamp voltage of
0.49V will set the minimum inductor current, I
follows:
OUT
IN
V
I
R
I
I
L
OUT(MIN)
RMS
BURST
should be sized for a maximum current rating of:
IN
OSC
I
L
will be selected based on the ESR that is required to
= 2.7V to 4.2V, V
(
1
MHz
( )
(
4
3 08 10
1
= 100mA, f = 1MHz.
MHz
A
.
2 5
V
1 10
.
BURST
•
)( . )
V
•
2 5
4 2
1 6
2 5
)( .
.
.
.
IN
6
0 47
U
V
V
A
V
11
and SV
– .
–
0 383
OUT
4 2
2 5
10
1
H
U
.
.
–
)
k
IN
= 2.5V, I
V
V
2 5
4 2
.
.
V
1
pins with two 22 F capaci-
–
298
–
V
V
1 1 96
2 5
4 2
6 9
0 6
W
.
.
.
.
k
OUT(MAX)
V
V
A
V
.
0 63
.
A
RMS
2 15
1 23
H
.
.
= 4A,
U
BURST
A
A
IN
:
, as
If we set the sum of R2 and R3 to 200k, then the following
equations can be solved:
The two equations shown above result in the following
values for R2 and R3: R2 = 78.7k , R3 = 124k. The value
of R1 can now be determined by solving the following
equation.
A value of 432k will be selected for R1. Figure 4 shows the
complete schematic for this design example.
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC3414. Check the following in your layout:
1. A ground plane is recommended. If a ground plane layer
is not used, the signal and power grounds should be
segregated with all small signal components returning to
the SGND pin at one point which is then connected to the
PGND pin close to the LTC3414.
2. Connect the (+) terminal of the input capacitor(s), C
as close as possible to the PV
provides the AC current into the internal power MOSFETs.
3. Keep the switching node, SW, away from all sensitive
small signal nodes.
4. Flood all unused areas on all layers with copper.
Flooding with copper will reduce the temperature rise of
power components. You can connect the copper areas to
any DC net (PV
DC rail in your system).
5. Connect the V
The resistor divider must be connected between V
and SGND.
R
1
1
R
1 432
2
R
R
202 7
2
3
R
R
3 200
1
.
k
0 49
k
0 8
.
.
IN
V
FB
, SV
2 5
0 8
V
k
.
.
pin directly to the feedback resistors.
V
V
IN
, V
OUT
, PGND, SGND, or any other
IN
pin. This capacitor
OUT
3414f
IN
,