SC16C2552 Philips Semiconductors, SC16C2552 Datasheet - Page 10

• Manufacturer Part Number: SC16C2552
• Description: Dual UART with 16-byte transmit and receive FIFOs
• Manufacturer: Philips Semiconductors

Philips Semiconductors
9397 750 11636
Product data
6.6 DMA operation
6.7 Loop-back mode
The SC16C2552 FIFO trigger level provides additional flexibility to the user for block
mode operation. LSR[5,6] provide an indication when the transmitter is empty or has
an empty location(s). The user can optionally operate the transmit and receive FIFOs
in the DMA mode (FCR[3]). When the transmit and receive FIFOs are enabled and
the DMA mode is de-activated (DMA Mode 0), the SC16C2552 activates the interrupt
output pin for each data transmit or receive operation. When DMA mode is activated
(DMA Mode 1), the user takes the advantage of block mode operation by loading or
unloading the FIFO in a block sequence determined by the receive trigger level and
the transmit FIFO. In this mode, the SC16C2552 sets the interrupt output pin when
characters in the transmit FIFO is below 16, or the characters in the receive FIFOs
are above the receive trigger level.
The internal loop-back capability allows on-board diagnostics. In the loop-back mode,
the normal modem interface pins are disconnected and reconfigured for loop-back
internally. MCR[0-3] register bits are used for controlling loop-back diagnostic testing.
In the loop-back mode, INT enable and MCR[2] in the MCR register (bits 2-3) control
the modem RI and CD inputs, respectively. MCR signals DTR and RTS (bits 0-1) are
used to control the modem CTS and DSR inputs, respectively. The transmitter output
(TX) and the receiver input (RX) are disconnected from their associated interface
pins, and instead are connected together internally (see
CD, and RI are disconnected from their normal modem control inputs pins, and
instead are connected internally to DTR, RTS, INT enable, and MCR[2]. Loop-back
test data is entered into the transmit holding register via the user data bus interface,
D0-D7. The transmit UART serializes the data and passes the serial data to the
receive UART via the internal loop-back connection. The receive UART converts the
serial data back into parallel data that is then made available at the user data
interface D0-D7. The user optionally compares the received data to the initial
transmitted data for verifying error-free operation of the UART TX/RX circuits.
In this mode, the receiver and transmitter interrupts are fully operational. The Modem
Control Interrupts are also operational. However, the interrupts can only be read
using lower four bits of the Modem Status Register (MSR[0-3]) instead of the four
Modem Status Register bits 4-7. The interrupts are still controlled by the IER.
Rev. 03 — 20 June 2003
Dual UART with 16-byte transmit and receive FIFOs
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Figure
SC16C2552
4). The CTS, DSR,
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