SC16C2552 Philips Semiconductors, SC16C2552 Datasheet - Page 4

• Manufacturer Part Number: SC16C2552
• Description: Dual UART with 16-byte transmit and receive FIFOs
• Manufacturer: Philips Semiconductors

Philips Semiconductors
Table 2:
9397 750 11636
Product data
Symbol
INTA, INTB
IOR
IOW
MFA, MFB
RESET
TXRDYA,
TXRDYB
V
XTAL1
XTAL2
CDA, CDB
CC
Pin description
Pin
34, 17
24
20
35, 19
21
1, 32
33, 44
11
13
42, 30
Type
O
I
I
O
I
O
I
I
O
I
…continued
Description
Interrupt A, B (Active-HIGH). This function is associated with individual channel
interrupts, INTA, INTB. INTA, INTB are enabled when MCR bit 3 is set to a logic 1,
interrupts are enabled in the interrupt enable register (IER), and when an interrupt
condition exists. Interrupt conditions include: receiver errors, available receiver buffer
data, transmit buffer empty, or when a modem status flag is detected.
Read strobe (Active-LOW). A logic 0 transition on this pin will load the contents of an
internal register defined by address bits A0-A2 onto the SC16C2552 data bus (D0-D7)
for access by external CPU.
Write strobe (Active-LOW). A logic 0 transition on this pin will transfer the contents of
the data bus (D0-D7) from the external CPU to an internal register that is defined by
address bits A0-A2.
Multi-Function A, B. This function is associated with an individual channel function, ‘A’
or ‘B’. User programmable bits 1-2 of the Alternate Function Register (AFR), selects a
signal function or output on these pins. OP2 (interrupt enable), BAUDOUT, and RXRDY
are signal functions that may be selected by the AFR. These signal functions are
described as follows:
Reset (Active-HIGH). A logic 1 on this pin will reset the internal registers and all the
outputs. The UART transmitter output and the receiver input will be disabled during
reset time. (See
details.)
Transmit Ready A, B (Active-LOW). These outputs provide the TX FIFO/THR status
for individual transmit channels (A-B). TXRDYn is primarily intended for monitoring
DMA mode 1 transfers for the transmit data FIFOs. An individual channel’s TXRDYA,
TXRDYB buffer ready status is indicated by logic 0, i.e., at least one location is empty
and available in the FIFO or THR. This pin goes to a logic 1 when there are no more
empty locations in the FIFO or THR. This signal can also be used for single mode
transfers (DMA mode 0).
Power supply input.
Crystal or external clock input. Functions as a crystal input or as an external clock
input. A crystal can be connected between this pin and XTAL2 to form an internal
oscillator circuit. Alternatively, an external clock can be connected to this pin to provide
custom data rates. (See
Output of the crystal oscillator or buffered clock. (See also XTAL1.) Crystal
oscillator output or buffered clock output. Should be left open if an external clock is
connected to XTAL1.
Carrier Detect (Active-LOW). These inputs are associated with individual UART
channels A through B. A logic 0 on this pin indicates that a carrier has been detected by
the modem for that channel.
OP2. When OP2 (interrupt output enable function) is selected, the MF pin is a logic 1
when INTA, INTB is set to the 3-State mode (disabled), or a logic 0 when INTA, INTB
is enabled. (See MCR[3].) A logic 1 is the default signal condition that is available
following a master reset or power-up.
BAUDOUT. When BAUDOUT function is selected, the 16 baud rate clock output is
available at this pin.
RXRDY. RXRDY is primarily intended for monitoring DMA mode 1 transfers for the
receive data FIFOs. A logic 0 indicates there is receive data to read/unload, i.e.,
receive ready status with one or more RX characters available in the FIFO/RHR. This
pin is a logic 1 when the FIFO/RHR is empty or when the programmed trigger level
has not been reached. This signal can also be used for single mode transfers (DMA
mode 0).
Rev. 03 — 20 June 2003
Section 7.11 “SC16C2552 external reset conditions”
Section 6.5 “Programmable baud rate
Dual UART with 16-byte transmit and receive FIFOs
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
SC16C2552
generator”.)
for initialization
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