DS2432X Dallas Semiconducotr, DS2432X Datasheet - Page 7

• Manufacturer Part Number: DS2432X
• Description: 1k-Bit Protected 1-Wire EEPROM with SHA-1 Engine
• Manufacturer: Dallas Semiconducotr

PRELIMINARY
DS2432
8 bytes, especially if the data is to be loaded as a secret. If the master sends less than eight data bytes and
does not read back the scratchpad for verification, parts of the new secret may be random data that is
unknown to the master. Only full data bytes are accepted. If the last data byte is incomplete its content
will be ignored and the partial byte flag PF will be set.
When executing the Write Scratchpad command the CRC generator inside the DS2432 (see Figure 12)
calculates a CRC of the entire data stream, starting at the command code and ending at the last data byte
as sent by the master. This CRC is generated using the CRC16 polynomial by first clearing the CRC
generator and then shifting in the command code (0FH) of the Write Scratchpad command, the Target
Addresses (TA1 and TA2), and all the data bytes. Note that the CRC16 calculation is performed with the
actual TA1 sent by the master even though the DS2432 will set TA1 bits T2..T0 to 000b for the actual
Write Scratchpad command. The master may end the Write Scratchpad command at any time. However,
if the scratchpad is filled to its capacity, the master may send 16 read time slots and will receive the CRC
generated by the DS2432.
If a Write Scratchpad is attempted with a target address in data memory (00h-7Fh) or the register page
(88h to 8Fh), then a subsequent Read Scratchpad command will read AAh or 55h for addresses that are
write-protected rather than the value that was written in the Write Scratchpad command. Similarly, if the
target address is within page 1 and the page is in EPROM mode, the read-back from the scratchpad will
produce data that is the logical AND of the original scratchpad data and the current content of the target
memory area.
Read Scratchpad [AAh]
The Read Scratchpad command allows verifying the target address and the integrity of the scratchpad
data. After issuing the command code, the master begins reading. The first two bytes will be the target
address with T2 to T0 = 0. The next byte will be the ending offset/data status byte (E/S) followed by the
scratchpad data, which may be different from what the master has originally sent. This is of particular
importance if the target address is the secret, the register page or page 1 in EPROM mode. The master
should read through the end of the scratchpad after which it will receive the inverted CRC. This is based
on data as it was sent by the DS2432. If the master continues reading after the CRC all data will be
logic 1’s.
Load First Secret [5Ah]
The Load First Secret command is used to replace the device’s current secret with the contents of the
scratchpad, provided that the secret is not write-protected. This command does not require the knowledge
of the device’s current secret. Before the Load First Secret command can be used the master must have
written the new secret to the scratchpad using the starting address of the secret (0080h). After issuing the
Load First Secret command, the master must provide a 3-byte authorization pattern, which should have
been obtained by an immediately preceding Read Scratchpad command. This 3-byte pattern must exactly
match the data contained in the three address registers (TA1, TA2, E/S, in that order). If the pattern
matches and the secret is not write-protected, the AA (Authorization Accepted) flag will be set and the
copy will begin. All eight bytes of scratchpad contents will be copied to the secret’s memory location.
The device-internal data transfer takes 10 ms maximum during which the voltage on the 1-Wire bus must
not fall below 2.8V. A pattern of alternating 1’s and 0’s will be transmitted after the data has been copied
until the master issues a reset pulse.
Instead of using Load First Secret, a new secret alternatively be loaded with the Copy Scratchpad
command. However, this approach requires the knowledge of the current secret and the computation of a
160-bit MAC.
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