EPM570 Altera, EPM570 Datasheet - Page 90

• Manufacturer Part Number: EPM570
• Description: MAX II Device Family
• Manufacturer: Altera

Timing Model & Specifications
5–28
MAX II Device Handbook, Volume 1
Notes to
(1)
(2)
t
t
t
t
t
t
t
t
JPCO
JPZX
JPXZ
JSSU
JSH
JSCO
JSZX
JSXZ
Table 5–34. MAX II JTAG Timing Parameters (Part 2 of 2)
Minimum clock period specified for 10 pF load on the TDO pin. Larger loads on TDO will degrade the maximum
TCK frequency.
This specification is shown for 3.3-V LVTTL/LVCMOS and 2.5-V LVTTL/LVCMOS operation of the JTAG pins. For
1.8-V LVTTL/LVCMOS and 1.5-V LVCMOS, the t
values at 35 ns.
Symbol
Table
5–34:
JTAG port clock to
output
JTAG port high
impedance to valid
output
JTAG port valid
output to high
impedance
Capture register
setup time
Capture register hold
time
Update register clock
to output
Update register high
impedance to valid
output
Update register valid
output to high
impedance
Parameter
(2)
(2)
(2)
Core Version a.b.c variable
JPSU
Min
10
minimum is 6 ns and t
8
JPCO
Max
15
15
15
25
25
25
, t
JPZX
, and t
JPXZ
Altera Corporation
December 2004
are maximum
Unit
ns
ns
ns
ns
ns
ns
ns
ns