LTC4261 LINER [Linear Technology], LTC4261 Datasheet - Page 24

• Manufacturer Part Number: LTC4261
• Description: Negative Voltage Hot Swap Controllers with ADC and I2C Monitoring
• Manufacturer: LINER [Linear Technology]

LTC4261/LTC4261-2
APPLICATIONS INFORMATION
reset to allow normal communication after the stuck-low
condition is cleared. When the SCL pin and the SDAI pin
are held low alternatively, if the ORed low period of SCL
and SDAI exceeds 66ms before the timer reset condi-
tion (both SCL and SDAI are high) occurs, the stuck-bus
timer will expire and the I
I
Any of eight distinct I
ing the three-state pins ADR0 and ADR1, as shown in
Table 1. Note that the confi guration of ADR0 = L and ADR1
= H is used to enable the single-wire broadcasting mode.
For the eight I
B4 are confi gured to (001) and the least signifi cant bit B0
is the R/W bit. In addition, the LTC4261/LTC4261-2 will
respond to two special addresses. Address (0011 111)
is a mass write used to write to all LTC4261/LTC4261-2s,
regardless of their individual address settings. Address
(0001 100) is the SMBus Alert Response Address. If the
LTC4261/LTC4261-2 are pulling low on the ALERT pin,
it will acknowledge this address using the SMBus Alert
Response Protocol.
Acknowledge
The acknowledge signal is used for handshaking between
the transmitter and the receiver to indicate that the last
byte of data was received. The transmitter always re-
leases the SDA line during the acknowledge clock pulse.
When the slave is the receiver, it must pull down the SDA
line so that it remains LOW during this pulse to acknowl-
edge receipt of the data. If the slave fails to acknowl-
edge by leaving SDA HIGH, then the master can abort
the transmission by generating a STOP condition. When
the master is receiving data from the slave, the master
must pull down the SDA line during the clock pulse to
indicate receipt of the data. After the last byte has been
received the master will leave the SDA line HIGH (not
acknowledge) and issue a STOP condition to terminate
the transmission.
Write Protocol
The master begins communication with a START con-
dition followed by the seven bit slave address and the
R/W bit set to zero. The addressed LTC4261/LTC4261-2
24
2
C Device Addressing
2
C bus addresses, address bits B6, B5 and
2
C bus addresses are selectable us-
2
C state machine is reset.
acknowledge this and then the master sends a command
byte which indicates which internal register the master
wishes to write. The LTC4261/LTC4261-2 acknowledge
this and then latch the lower four bits of the command
byte into its internal Register Address pointer. The master
then delivers the data byte and the LTC4261/LTC4261-2
acknowledge once more and latch the data into its inter-
nal register. The transmission is ended when the master
sends a STOP condition. If the master continues sending
a second data byte, as in a Write Word command, the
second data byte will be acknowledged by the LTC4261/
LTC4261-2 but ignored.
Read Protocol
The master begins a read operation with a START con-
dition followed by the seven bit slave address and the
R/W bit set to zero. The addressed LTC4261/LTC4261-2
acknowledge this and then the master sends a command
byte that indicates which internal register the master
wishes to read. The LTC4261/LTC4261-2 acknowledge
this and then latch the lower four bits of the command
byte into its internal Register Address pointer. The mas-
ter then sends a repeated START condition followed by
the same seven bit address with the R/W bit now set to
one. The LTC4261/LTC4261-2 acknowledge and send the
contents of the requested register. The transmission is
ended when the master sends a STOP condition. If the
master acknowledges the transmitted data byte, as in a
Read Word command, the LTC4261/LTC4261-2 will re-
peat the requested register as the second data byte. Note
that the Register Address pointer is not cleared at the
end of the transaction. Thus the Receive Byte protocol
can be used to repeatedly read a specifi c register.
Alert Response Protocol
The LTC4261/LTC4261-2 implement the SMBus Alert
Response Protocol as shown in Figure 14. If enabled
to do so through the ALERT register C, the LTC4261/
LTC4261-2 will respond to faults by pulling the ALERT
pin low. Multiple LTC4261/LTC4261-2s can share a com-
mon ALERT line and the protocol allows a master to de-
termine which LTC4261/LTC4261-2s are pulling the line
low. The master begins by sending a START bit followed
by the special Alert Response Address (0001 100)b with
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