LTC4261 LINER [Linear Technology], LTC4261 Datasheet - Page 9

• Manufacturer Part Number: LTC4261
• Description: Negative Voltage Hot Swap Controllers with ADC and I2C Monitoring
• Manufacturer: LINER [Linear Technology]

PIN FUNCTIONS
PGIO (Pin 28/Pin 21): General Purpose Input/Output. Open-
drain logic output and logic input. Defaults to pull low a
timer delay after the PG pin goes low to indicate a second
power good output. Confi gure according to Table 6.
RAMP (Pin 18/Pin 12): Inrush Current Ramp Control
Pin. The inrush current is set by placing a capacitor (C
between the RAMP pin and the drain terminal of the FET.
At start-up, the GATE pin is pulled up by I
pass transistor begins to turn on. A current, I
fl ows through C
The value of I
When the SS pin reaches its clamp voltage (2.56V), I
= 20µA. The ramp rate of V
set the inrush current: I
SCL (Pin 6/Pin 3): Serial Bus Clock Input. Data at the
SDAI pin is shifted in and data at the SDAO pin is shifted
out on rising edges of SCL. This is a high impedance pin
that is generally connected to the output of the incoming
optoisolator driven by the SCL port of the master controller.
An external pull-up resistor or current source is required.
Pull up to INTV
SDAI (Pin 5/Pin 2): Serial Bus Data Input. This is a high
impedance input pin used for shifting in command or
data bits. An external pull-up resistor or current source is
required. Normally connected to the output of the incoming
optoisolator that is driven by the SDA port of the master
controller. Pull up to INTV
SDAO (Pin 4/Pin 1): Serial Bus Data Output. Open-drain
output used for sending data back to the master controller
or acknowledging a write operation. An external pull-up
resistor or current source is required. Normally connected
to the input of the outgoing optoisolator that outputs to
the SDA port of the master controller. In the single-wire
broadcast mode, the SDAO pin sends out selected data
that is encoded with an internal clock.
SENSE (Pin 14/Pin 9): Current Limit Sense Input. Load
current through the external sense resistor (R
tored and controlled by an active current limit amplifi er to
50mV/R
timer starts and turns off the pass transistor after 530µs. In
the event of a catastrophic short circuit, if V
150mV, a fast response comparator immediately pulls the
GATE pin down to turn off the N-channel FET.
S
. Once V
RAMP
CC
R
to ramp down the output voltage V
if unused.
SENSE
is controlled by the SS pin voltage.
INRUSH
reaches 50mV, a circuit breaker
CC
(SSOP/QFN)
OUT
if unused.
= (C
and the load capacitor C
L
/C
R
) • I
GATE(UP)
SENSE
RAMP
S
RAMP
) is moni-
until the
crosses
.
, then
RAMP
OUT
R
L
)
.
SS (Pin 19/Pin 13): Soft-Start Input. Connect a capacitor to
this pin to control the rate of rise of inrush current (dI/dt)
during start-up. An internal 10µA current source charging
the external soft-start capacitor (C
ramp. This voltage is converted to a current to charge the
GATE pin up and to ramp the output voltage down. The
SS pin is internally clamped to 2.56V limiting I
11.5µA and I
the SS pin ramps from 0V to 2.56V in 220µs.
TMR (Pin 20/Pin 14): Delay Timer Input. Connect a capaci-
tor (C
when power good outputs pull down, during PGI check and
when auto-retrying after faults (except overvoltage fault).
Internal pull-up currents of 10µA and 5µA and pull-down
currents of 5µA and 12mA confi gure the delay periods as
multiples of a nominal delay of 256ms • C
for start-up and auto-retry following undervoltage or power
bad fault are the same as the nominal delay. Delays for
sequenced power good outputs are twice of the nominal
delay. Delays for PGI check and auto-retry following over-
current fault are four times the nominal delay.
UVH (Pin 9/Pin 6): Undervoltage High Level Input. Con-
nect this pin to an external resistive divider from V
the voltage at the UVH pin rises above 2.56V the pass
transistor is allowed to turn on. A small capacitor at this
pin prevents transients and switching noise from affecting
the UVH threshold. Connect to INTV
UVL (Pin 8/Pin 5): Undervoltage Low Level Input. Con-
nect this pin to an external resistive divider from V
the voltage at the UVL pin drops below 2.291V, the pass
transistor is turned off and the power good outputs go
high impedance. Pulling this pin below 1.21V resets faults
and allows the pass transistor to turn back on. Connect
to INTV
V
Device Ground. Connect this pin to the negative side of
the power supply.
V
pin to the positive supply through a dropping resistor. An
internal shunt regulator clamps V
undervoltage lockout (UVLO) circuit holds the GATE low
until V
tor to V
EE
IN
(Pin 21/Pin 15): Positive Supply Input. Connect this
(Pin 13/Pin 8): Negative Supply Voltage Input and
TMR
IN
EE
CC
is above 9V. Bypass this pin with a 1µF capaci-
) to this pin to create timing delays at start-up,
.
if unused.
RAMP
LTC4261/LTC4261-2
to 20µA. If the SS capacitor is absent,
IN
SS
at 11.2V. An internal
CC
) creates a voltage
if unused.
TMR
/µF. Delays
GATE(UP)
EE
EE
42612fb
9
. If
. If
to