LMK01000ISQ NSC [National Semiconductor], LMK01000ISQ Datasheet - Page 10

• Manufacturer Part Number: LMK01000ISQ
• Description: 1.6 GHz High Performance Clock Buffer, Divider, and Distributor
• Manufacturer: NSC [National Semiconductor]

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2.0 General Programming
Information
The
grammed using several 32-bit registers which control the
device's operation. The registers consist of a data field and
an address field. The last 4 register bits, ADDR[3:0] form the
address field. The remaining 28 bits form the data field DATA
[27:0].
During programming, LEuWire is low and serial data is
clocked in on the rising edge of clock (MSB first). When
LEuWire goes high, data is transferred to the register bank
selected by the address field. Only registers R0 to R7 and R14
need to be programmed for proper device operation.
It is required to program register R14.
2.1 RECOMMENDED PROGRAMMING SEQUENCE
The recommended programming sequence involves pro-
gramming R0 with the reset bit set (RESET = 1) to ensure the
device is in a default state. It is not necessary to program R0
again, but if R0 is programmed again, the reset bit is pro-
grammed clear (RESET = 0). An example programming se-
quence is shown below.
•
•
•
Program R0 with the reset bit set (RESET = 1). This
ensures the device is in a default state. When the reset bit
is set in R0, the other R0 bits are ignored.
— If R0 is programmed again, the reset bit is programmed
Program R0 to R7 as necessary with desired clocks with
appropriate enable, mux, divider, and delay settings.
Program R14 with global clock output bit, power down
setting.
— R14 must be programmed in accordance with the
LMK01000/LMK01010/LMK01020
clear (RESET = 0).
register map as shown in the register map (see 2.2).
device
is
pro-
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