LMK01000ISQ NSC [National Semiconductor], LMK01000ISQ Datasheet - Page 12

• Manufacturer Part Number: LMK01000ISQ
• Description: 1.6 GHz High Performance Clock Buffer, Divider, and Distributor
• Manufacturer: NSC [National Semiconductor]

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2.3 REGISTER R0 to R7
Registers R0 through R7 control the eight clock outputs. Reg-
ister R0 controls CLKout0, Register R1 controls CLKout1, and
so on. There is one additional bit in register R0 called RESET.
2.3.1 RESET Bit -- R0 only
This bit is only in register R0. The use of this bit is optional
and it should be set to '0' if not used. Setting this bit to a '1'
forces all registers to their power-on-reset condition and
therefore automatically clears this bit. If this bit is set, all other
R0 bits are ignored and R0 needs to be programmed again if
used with its proper values and RESET = 0.
2.3.2 CLKoutX_MUX[1:0] -- Clock Output Multiplexers
These bits control the Clock Output Multiplexer for each clock
output. Changing between the different modes changes the
blocks in the signal path and therefore incurs a delay relative
to the Bypassed mode. The different MUX modes and asso-
ciated delays are listed below.
2.3.3 CLKoutX_DIV[7:0] -- Clock Output Dividers
These bits control the clock output divider value. In order for
these dividers to be active, the respective CLKoutX_MUX
(See 2.3.2) bit must be set to either "Divided" or "Divided and
Delayed" mode. After all the dividers are programed, the
SYNC* pin must be used to ensure that all edges of the clock
outputs are aligned (See 1.7). By adding the divider block to
the output path a fixed delay of approximately 100 ps is in-
curred.
The actual Clock Output Divide value is twice the binary value
programmed as listed in the table below.
RESET
CLKoutX_MUX
CLKoutX_EN
CLKoutX_DIV
CLKoutX_DLY
CLKin_SELECT
EN_CLKout_Global
POWERDOWN
CLKoutX_MUX
0
0
[1:0]
0
0
Bit Name
0
1
2
3
CLKoutX_DIV[7:0]
0
0
0
0
Bypassed (default)
0
0
Divided and
Delayed
Delayed
Divided
Mode
Bit Value
0
0
Default
0
0
0
1
0
0
1
0
0
0
Default Register Settings after Power-on-Reset
No reset, normal operation
Bypassed
Disabled
Divide by 2
0 ps
CLKin1
Normal - CLKouts normal
Normal - Device active
0
1
(In addition to the
(In addition to the
Bypassed Mode
Added Delay
programmed
programmed
Relative to
Clock Output
Divider value
100 ps
400 ps
500 ps
2 (default)
delay)
delay)
0 ps
Invalid
Bit State
12
Aside from this, the functions of these bits are identical. The
X in CLKoutX_MUX, CLKoutX_DIV, CLKoutX_DLY, and
CLKoutX_EN denote the actual clock output which may be
from 0 to 7.
2.3.4 CLKoutX_DLY[3:0] -- Clock Output Delays
These bits control the delay stages for each clock output. In
order for these delays to be active, the respective
CLKoutX_MUX (See 2.3.2) bit must be set to either "Delayed"
or "Divided and Delayed" mode. By adding the delay block to
the output path a fixed delay of approximately 400 ps is in-
curred in addition to the delay shown in the table below.
2.3.5 CLKoutX_EN bit -- Clock Output Enables
These bits control whether an individual clock output is en-
abled or not. If the EN_CLKout_Global bit is set to zero or if
GOE pin is held low, all CLKoutX_EN bit states will be ignored
and all clock outputs will be disabled.
0
0
0
0
1
.
CLKoutX_DLY[3:0]
Reset to power on defaults
CLKoutX mux mode
CLKoutX enable
CLKoutX clock divide
CLKoutX clock delay
Select CLKin0 or CLKin1
Global clock output enable
Device power down
0
0
0
0
1
.
CLKoutX_DIV[7:0]
Bit Description
0
0
0
0
1
.
10
11
12
13
14
15
0
1
2
3
4
5
6
7
8
9
0
0
0
0
1
.
0
0
0
0
1
.
0
0
1
1
1
.
1
1
0
0
1
.
Register
R0 to R7
Delay (ps)
0 (default)
0
1
0
1
1
.
R14
R0
1050
1200
1350
1500
1650
1800
1950
2100
2250
150
300
450
600
750
900
Clock Output
Divider value
Location
510
10
...
4
6
8
18:17
15:8
7:4
Bit
31
16
28
27
26