LMK01000ISQ NSC [National Semiconductor], LMK01000ISQ Datasheet - Page 13

• Manufacturer Part Number: LMK01000ISQ
• Description: 1.6 GHz High Performance Clock Buffer, Divider, and Distributor
• Manufacturer: NSC [National Semiconductor]

2.4 REGISTER R9 and R14
The LMK01000 family requires register R14 to be pro-
grammed as shown in the register map (see 2.2). R9 only
needs to be programmed if Vboost is set to 1.
2.4.1 Vboost - Voltage Boost Bit
Enabling this bit sets all clock outputs in voltage boost mode
which increases the voltage at these outputs. This can im-
prove the noise floor performance of the output, but also
increases current consumption, and can cause the outputs to
be too high to meet the LVPECL/LVDS specifications.
CLKoutX_EN bit
Vboost
bit
0
1
0
1
Recommended to
hit voltage level
specifications for
LVPECL/LVDS
Voltage May
overdrive LVPECL/
LVDS
specifications, but
noise floor is about
2-4 dB better and
current
consumption is
increased
f
CLKoutX
MHz
GOE pin = High / No
EN_CLKout_Global
< 1300
Conditions
Connect 1
bit = 1
Insufficient voltage level for
LVDS/LVPECL
specifications, but saves
current
Voltage is
sufficient for
LVDS/
LEVPECL
specifications
. Current
consumption
is increased,
but noise floor
is about the
same.
1300 MHz
1500 MHz
f
CLKoutX
<
Disabled (default)
≤
CLKoutX State
Insufficient
voltage for
LVDS/
LVPECL
specifications
, but still
higher than
when
Vboost=0.
Increased
current
consumption.
1500 MHz
Enabled
1600 MHz
f
CLKoutX
≤
≤
13
2.4.2 POWERDOWN Bit -- Device Power Down
This bit can power down the device. Enabling this bit powers
down the entire device and all blocks, regardless of the state
of any of the other bits or pins.
2.4.3 INPUT_MUX Bit -- Device CLKin Select
This bit determines which CLKin pin is used.
POWERDOWN bit
CLKin bit
0
1
0
1
Entire Device Powered Down
Normal Operation (default)
CLKin1 (default)
CLKin0
Mode
Mode
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