AD9200LQFP-EVAL AD [Analog Devices], AD9200LQFP-EVAL Datasheet - Page 12

• Manufacturer Part Number: AD9200LQFP-EVAL
• Description: Complete 10-Bit, 20 MSPS, 80 mW CMOS A/D Converter
• Manufacturer: AD [Analog Devices]

AD9200
EXTERNAL REFERENCE OPERATION
Using an external reference may provide more flexibility and
improve drift and accuracy. Figures 21 through 23 show ex-
amples of how to use an external reference with the AD9200.
To use an external reference, the user must disable the internal
reference amplifier by connecting the REFSENSE pin to VDD.
The user then has the option of driving the VREF pin, or driv-
ing the REFTS and REFBS pins.
The AD9200 contains an internal reference buffer (A2), that
simplifies the drive requirements of an external reference. The
external reference must simply be able to drive a 10 k load.
Figure 21 shows an example of the user driving the top and bottom
references. REFTS is connected to a low impedance 2 V source
and REFBS is connected to a low impedance 1 V source. REFTS
and REFBS may be driven to any voltage within the supply as
long as the difference between them is between 1 V and 2 V.
Figure 22 shows an example of an external reference generating
2.5 V at the shorted REFTS and REFBS inputs. In this in-
stance, a REF43 2.5 V reference drives REFTS and REFBS. A
resistive divider generates a 1 V VREF signal that is buffered by
A3. A3 must be able to drive a 10 k , capacitive load. Choose
this op amp based on noise and accuracy requirements.
Figure 23a shows an example of the external references driving
the REFTF and REFBF pins that is compatible with the
AD876. REFTS is shorted to REFTF and driven by an external
4 V low impedance source. REFBS is shorted to REFBF and
driven by a 2 V source. The MODE pin is connected to GND
in this configuration.
Figure 21. External Reference Mode—1 V p-p Input Span
2V
1V
AVDD
0.1 F
2V
1V
Figure 22. External Reference Mode—1 V p-p Input
Span 2.5 V
3.0V
2.5V
2.0V
10 F
REF43
REFBS
SENSE
REFTS
MODE
1k
REF
1.5k
AIN
A3
CM
+5V
0.1 F
10k
10k
AVDD/2
1.0 F
10k
10k
A2
AVDD
SHA
0.1 F
0.1 F
CORE
A/D
AIN
REFTS
REFBS
REFSENSE
VREF
MODE
AD9200
AD9200
4.2k
TOTAL
REFBF
REFTF
AVDD
0.1 F
REFTF
REFBF
0.1 F
0.1 F
0.1 F
AVDD
10 F
0.1 F
0.1 F
10 F
–12–
Figure 23b. Kelvin Connected Reference Using the AD9200
STANDBY OPERATION
The ADC may be placed into a powered down (sleep) mode by
driving the STBY (standby) pin to logic high potential and
holding the clock at logic low. In this mode the typical power
drain is approximately 4 mW. If there is no connection to the
STBY pin, an internal pull-down circuit will keep the ADC in a
“wake-up” mode of operation.
The ADC will “wake up” in 400 ns (typ) after the standby pulse
goes low.
CLAMP OPERATION
The AD9200ARS and AD9200KST parts feature an optional
clamp circuit for dc restoration of video or ac coupled signals.
Figure 24 shows the internal clamp circuitry and the external
control signals needed for clamp operation. To enable the
clamp, apply a logic high to the CLAMP pin. This will close
the switch SW1. The clamp amplifier will then servo the volt-
age at the AIN pin to be equal to the clamp voltage applied at
the CLAMPIN pin. After the desired clamp level is attained,
SW1 is opened by taking CLAMP back to a logic low. Ignoring
the droop caused by the input bias current, the input capacitor
CIN will hold the dc voltage at AIN constant until the next
clamp interval. The input resistor RIN has a minimum recom-
mended value of 10 , to maintain the closed-loop stability of
the clamp amplifier.
The allowable voltage range that can be applied to CLAMPIN
depends on the operational limits of the internal clamp ampli-
fier. When operating off of 3 volt supplies, the recommended
clamp range is between 0.5 volts and 2.0 volts.
REFB
REFT
Figure 23a. External Reference—2 V p-p Input Span
4V
2V
2
3
6
5
4V
2V
+5V
4
8
7
6
0.1 F
C4
0.1 F
C5
0.1 F
C3
0.1 F
10 F
C1
0.1 F
AVDD
0.1 F
0.1 F
C2
10 F
C6
0.1 F
VIN
REFTS
REFTF
REFBF
REFBS
VREF
REFSENSE
MODE
AD9200
REFTS
REFTF
REFBS
REFBF
AD9200
REV. E