AD5780ACPZ AD [Analog Devices], AD5780ACPZ Datasheet - Page 19

• Manufacturer Part Number: AD5780ACPZ
• Manufacturer: AD [Analog Devices]

Data Sheet
THEORY OF OPERATION
The
serial input, voltage output DAC. It operates from a V
voltage of 7.5 V to 16.5 V and a V
Data is written to the
serial interface. The
circuit that ensures the DAC output powers up to 0 V with the
V
DAC ARCHITECTURE
The architecture of the
sections. A simplified circuit diagram is shown in Figure 50.
The six MSBs of the 18-bit data-word are decoded to drive
63 switches, E0 to E62. Each of these switches connects one
of 63 matched resistors to either the buffered V
V
the S0 to S11 switches of a 12-bit voltage mode R-2R ladder
network.
Table 6. Input Shift Register Format
MSB
DB23
R/W
Table 7. Decoding the Input Shift Register
R/W
X
0
0
0
0
1
1
1
1
X is don’t care.
1
OUT
REFN
AD5780
pin clamped to AGND through a ~6 kΩ internal resistor.
voltage. The remaining 12 bits of the data-word drive
0
0
0
0
1
0
0
0
is a high accuracy, fast settling, single, 18-bit,
AD5780
Register Address
AD5780
AD5780
DB22
0
0
1
1
0
0
1
1
incorporates a power-on reset
in a 24-bit word format via a 3-wire
consists of two matched DAC
SS
supply of −16.5 V to −2.5 V.
0
1
0
1
0
1
0
1
REFP
DB21
Description
No operation (NOP). Used in readback operations.
Write to the DAC register.
Write to the control register.
Write to the clearcode register.
Write to the software control register.
Read from the DAC register.
Read from the control register.
Read from the clearcode register.
Register address
or buffered
DD
supply
Rev. C | Page 19 of 28
DB20
SERIAL INTERFACE
The
SDIN) that is compatible with SPI, QSPI, and MICROWIRE
interface standards, as well as most DSPs (see
timing diagram).
Input Shift Register
The input shift register is 24 bits wide. Data is loaded into the
device MSB first as a 24-bit word under the control of a serial
clock input, SCLK, which can operate at up to 35 MHz. The
input register consists of a R/ W bit, three address bits, and
20 data bits as shown in
operation is shown in
V
V
REFN
REFP
AD5780
Figure 50. DAC Ladder Structure Serial Interface
has a 3-wire serial interface ( SYNC , SCLK, and
2R
12-BIT R-2R LADDER
DB19 to DB0
Register data
Figure 2
2R
S0
R
Table 6
2R
S1
R
.
...
...
. The timing diagram for this
2R
S11
SIX MSBs DECODED INTO
R
63 EQUAL SEGMENTS
2R
E62
Figure 2
E61
2R
...
...
AD5780
2R
E0
for a
V
OUT
LSB