AD5780ACPZ AD [Analog Devices], AD5780ACPZ Datasheet - Page 21

• Manufacturer Part Number: AD5780ACPZ
• Manufacturer: AD [Analog Devices]

Data Sheet
Asynchronous DAC Update
In this mode, LDAC is held high while data is being clocked
into the input shift register. The DAC output is asynchronously
updated by taking LDAC low after SYNC has been taken high.
The update now occurs on the falling edge of LDAC .
Reset Function ( RESET )
The
either by asserting the RESET pin or by using the reset function
in the software control register (see
is not used, hardwire it to IOV
Asynchronous Clear Function ( CLR )
The CLR pin is an active low clear that allows the output to be
cleared to a user defined value. The 18-bit clearcode value is
programmed to the clearcode register (see
necessary to maintain
to complete the operation (see
is returned high, the output remains at the clear value (if LDAC
Table 8. Hardware Control Pins Truth Table
LDAC
X
X
0
0
1
1
0
1
0
1
Table 9. DAC Register
MSB
DB23
R/W
R/W
1
X is don’t care.
X is don’t care.
1
1
AD5780
CLR
X
X
0
1
0
1
0
1
0
1
X
1
X
can be reset to its power-on state by two means:
DB22
0
RESET
0
1
1
1
1
1
1
1
1
1
1
1
CLR low for a minimum amount of time
CC
Figure 2
Function
The
The
The DAC register is loaded with the clearcode register value, and the output is set accordingly.
The output is set according to the DAC register value.
The DAC register is loaded with the clearcode register value, and the output is set accordingly.
The output is set according to the DAC register value.
The output remains at the clearcode register value.
The output remains set according to the DAC register value.
The output remains at the clearcode register value.
The DAC register is loaded with the clearcode register value and the output is set accordingly.
The DAC register is loaded with the clearcode register value and the output is set accordingly.
The output remains at the clearcode register value.
The output is set according to the DAC register value.
.
Register address
DB21
0
Table 13
AD5780
AD5780
). When the
Table 12
). If the
is in reset mode. The device cannot be programmed.
is returned to its power-on state. All registers are set to their default values.
). It is
DB20
1
CLR signal
RESET pin
Rev. C | Page 21 of 28
DB19 to DB2
DAC register data
18 bits of data
is high) until a new value is loaded to the DAC register. The
output cannot be updated with a new value while the CLR pin is
low. A clear operation can also be performed by setting the CLR
bit in the software control register (see
ON-CHIP REGISTERS
DAC Register
Table 9 outlines how data is written to and read from the DAC
register.
The following equation describes the ideal transfer function of
the DAC:
where:
V
V
D is the 18-bit code programmed to the DAC.
V
OUT
REFN
REFP
is the positive voltage applied at the V
is the negative voltage applied at the V
=
(
V
REFP
−
2
V
18
REFN
)
×
D
+
V
REFN
DB1
X
Table 13
1
REFP
REFN
input pin.
).
input pin.
AD5780
DB0
X
1
X
LSB