PCM1604 BURR-BROWN [Burr-Brown Corporation], PCM1604 Datasheet - Page 11

• Manufacturer Part Number: PCM1604
• Description: 24-Bit, 192kHz Sampling,6-Channel, Enhanced Multi-Level, Delta-Sigma DIGITAL-TO-ANALOG CONVERTER
• Manufacturer: BURR-BROWN [Burr-Brown Corporation]

TABLE I. System Clock Rates for Common Audio Sampling Frequencies.
FIGURE 1. System Clock Input Timing.
SYSTEM CLOCK AND RESET
FUNCTIONS
SYSTEM CLOCK INPUT
The PCM1604 and PCM1605 require a system clock for
operating the digital interpolation filters and multi-level
delta-sigma modulators. The system clock is applied at the
SCKI input (pin 38). Table I shows examples of system
clock frequencies for common audio sampling rates.
Figure 1 shows the timing requirements for the system clock
input. For optimal performance, it is important to use a clock
source with low phase jitter and noise. Burr-Brown’s
PLL1700 multi-clock generator is an excellent choice for
providing the PCM1604 system clock source.
To obtain optimal dynamic performance when operating
with a 192kHz sampling frequency, it is recommended that
only two channels be enabled for operation (V
V
setting bits DAC3 through DAC6 of control register 8 to
logic 1 state.
SYSTEM CLOCK OUTPUT
A buffered version of the system clock input is available at
the SCKO output (pin 39). SCKO can operate at either full
(f
may be programmed using the CLKD bit of Control Regis-
ter 9. The SCKO output pin can also be enabled or disabled
using the CLKE bit of Control Register 9. The default is
SCKO enabled.
NOTE: (1) The 768f
OUT
SCKI
SAMPLING FREQUENCY
2). The remaining four channels should be disabled by
) or half (f
176.4kHz
44.1kHz
88.2kHz
96kHz
16kHz
32kHz
48kHz
192
(f
S
)
S
SCKI
system clock rate is not supported for f
/2) rate. The SCKO output frequency
SCKI
12.2880
22.5792
24.5760
“H”
128f
“L”
—
—
—
—
—
S
System Clock Pulse Width High t
System Clock Pulse Width Low t
t
SCKIH
18.4320
33.8688
36.8640
192f
S
—
—
—
—
—
> 64kHz. (2) This system clock rate is not supported for the given sampling frequency.
OUT
S
1 and
t
SCKIH
SYSTEM CLOCK FREQUENCY (f
11
See Note 2
See Note 2
11.2896
12.2880
22.5792
24.5760
4.0960
8.1920
256f
POWER-ON AND EXTERNAL RESET FUNCTIONS
The PCM1604 includes a power-on reset function. Figure 2
shows the operation of this function.
The system clock input at SCKI should be active for at least
one clock period prior to V
active and V
enabled. The initialization sequence requires 1024 system
clocks from the time V
period, the PCM1604 will be set to its reset default state, as
described in the Mode Control Register section of this data
sheet.
The PCM1604 also includes an external reset capability
using the RST input (pin 37). This allows an external
controller or master reset circuit to force the PCM1604 to
initialize to its reset default state. For normal operation, RST
should be set to a logic ‘1’.
Figure 3 shows the external reset operation and timing. The
RST pin is set to logic ‘0’ for a minimum of 20ns. The RST
pin is then set to a logic ‘1’ state, which starts the initializa-
tion sequence, which lasts for 1024 system clock periods.
After the initialization sequence is completed, the PCM1604
will be set to its reset default state, as described in the Mode
Control Registers section of this data sheet.
The external reset is especially useful in applications where
there is a delay between PCM1604 power up and system
clock activation. In this case, the RST pin should be held at
a logic ‘0’ level until the system clock has been
activated.
S
SCKIL
SCKIH
(MHz)
f
SCKI
DD
See Note 2
See Note 2
: 7ns min
: 7ns min
PCM1604, PCM1605
12.2880
16.9344
18.4320
33.8688
36.8640
6.1440
384f
> 2.0V, the power-on reset function will be
S
SCKI
DD
)
DD
> 2.0V. After the initialization
= 2.0V. With the system clock
See Note 2
See Note 2
2.0V
0.8V
16.3840
22.5792
24.5760
45.1584
49.1520
8.1920
512f
S
See Note 1
See Note 1
See Note 2
See Note 2
36.8640
12.2880
24.5760
33.8688
768f
S
®